Pipelined architecture to decode parallel and serial concatenated codes
First Claim
1. A cascaded processor decoder for decoding encoded data, the decoder comprising:
- a plurality of decoder processors, including a first cascaded decoder processor and a second cascaded decoder processor;
a metric output of said first cascaded decoder connected to a metric input of said second cascaded decoder processor; and
a multiple-block memory connected to said decoder processors for storing encoded input data arranged in multiple data blocks.
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Abstract
The present invention provides a method and apparatus (400) for iteratively decoding data which has been encoded with contatenated codes. The apparatus (400) includes pipelined and cascaded decoder processors (406, 430 and 436) connected to a multiple block memory device (402), through a multiplexing and data control block (404). A data decision element (437) is provided for generating decoded output data. The method includes receiving encoded data (802) while data already received is processed iteratively by decoder processors in a pipelined fashion. Decoder processors are designated to perform particular iterations (810) of an iterative decoding process which are performed simultaneously. As a decoder processor completes processing its designated iteration on a block of data, the decoder processor outputs decoding information (808) to the decoding processor designated to perform the subsequent iteration. Upon completion of all iterations for a block of data, the method includes generating output (814) consisting of the decoded data block. The method provides that once processing is complete on a data block, the memory block is made available (816) for the storing of new encoded input data.
95 Citations
18 Claims
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1. A cascaded processor decoder for decoding encoded data, the decoder comprising:
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a plurality of decoder processors, including a first cascaded decoder processor and a second cascaded decoder processor;
a metric output of said first cascaded decoder connected to a metric input of said second cascaded decoder processor; and
a multiple-block memory connected to said decoder processors for storing encoded input data arranged in multiple data blocks. - View Dependent Claims (2, 3, 4, 5)
a plurality of multiplexers connected between said decoder processors and said memory, said multiplexers allowing any decoder processor to access any data block in said memory; and
a data decision element for generating decoded output data, said data decision element connected to said second cascaded decoder processor.
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5. The cascaded processor decoder of claim 1, further comprising:
at least one multiplexer randomly accessing a data block of said multiple-block memory.
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6. A cascaded processor decoder for iteratively decoding data, the decoder comprising:
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a plurality of decoder processors equal in number to a predetermined number of decoding iterations, said decoder processors including at least a first cascaded decoder processor and a second cascaded decoder processor;
a metric output of said first cascaded decoder processor connected to a metric input of said second cascaded decoder processor;
a multiple-block memory comprising data blocks at least equal in number to said decoder processors;
a plurality of multiplexers connected between said data blocks and said decoder processors, said multiplexers allowing said decoder processors to selectively access any of said data blocks; and
a data decision element for generating decoded output data, said data decision element connected to said second cascaded decoder processor. - View Dependent Claims (7, 8, 9)
a systematic bits section;
a first parity bits section; and
a second parity bits section.
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8. The cascaded processor decoder of claim 7 wherein each of said decoder processors comprise:
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a first decoder connected to a first data block including an associated systematic bits section and an associated first parity bits section;
a permuter connected to a metric output of said first decoder;
a second decoder connected to said first data block including an associated second parity bits section, said second decoder connected to an output of said permuter; and
an inverse permuter connected to a metric output of said second decoder.
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9. The cascaded processor decoder of claim 8, wherein said data decision element comprises:
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a delay element connected to a metric output of said first decoder of said second cascaded decoder processor;
an adder connected to an output of said delay element, said adder connected to an output of said inverse permuter of said second cascaded decoder processor;
a data decision processor connected to an output of said adder, said data decision processor including a decoded data bit output.
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10. A method for iteratively decoding encoded data using a predetermined total number of decoding iterations, the method comprising:
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receiving encoded data into a data block in a multiple-block memory;
accessing the encoded data in the data block by a first decoder processor through a plurality of multiplexers; and
iteratively decoding said encoded data a predetermined total number of times with said cascaded decoder processors. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
generating an output bit stream of decoded encoded data with a data decision element.
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12. The method for iteratively decoding encoded data of claim 10, wherein said step of iteratively decoding comprises iteratively decoding among at least two interconnected cascaded decoder processors.
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13. The method for iteratively decoding encoded data of claim 10, wherein said step of iteratively decoding comprises decoding at most one iteration on each of said cascaded decoder processors.
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14. The method for iteratively decoding encoded data of claim 10, wherein said step of iteratively decoding comprises:
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performing a first number of decoding iterations on said encoded data with a first decoder processor, and generating first resultant metrics;
passing said first resultant metrics to a second decoder processor;
accessing the encoded data in the data block by the second decoder processor through a plurality of multiplexers;
performing a second number of decoding iterations on said encoded data and first resultant metrics with a second decoder processor and generating second resultant metrics; and
passing said second resultant metrics to a third decoder processor.
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15. The method for iteratively decoding encoded data of claim 14, further comprising:
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performing a last decoding iteration with a last decoder processor, and generating last resultant metrics;
passing said last resultant metrics from said last decoder processor to a data decision element; and
performing data decisions with said data decision element.
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16. The method for iteratively decoding encoded data of claim 15 wherein said step of performing data decisions comprises generating decoded data based on a polarity of said last resultant metrics.
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17. The method for iteratively decoding encoded data of claim 15, wherein said step of generating last resultant metrics comprises:
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generating a first subset;
generating a second subset; and
generating said last resultant metrics by adding said first subset to said second subset.
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18. The method for iteratively decoding encoded data of claim 17 wherein said step of performing data decisions comprises generating decoded data based on a polarity of said last resultant metrics.
Specification