Lifetime-sensitive instruction scheduling mechanism and method

• US 6,305,014 B1
• Filed: 06/18/1998
• Issued: 10/16/2001
• Est. Priority Date: 06/18/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schmidt, William Jon, Roediger, Robert Ralph
• Primary Examiner(s): Elmore, Reba I.
• Application Number:
  US09/099,360
• Time in Patent Office: 1,216 Days
• Field of Search: 395/709, 395/708, 717/5, 717/6, 717/9
• US Class Current: 717/154
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836

Abstract

An instruction scheduler in an optimizing compiler schedules instructions in a computer program by determining the lifetimes of fixed registers in the computer program. By determining the lifetimes of fixed registers, the instruction scheduler can achieve a schedule that has a higher degree of parallelism by relaxing dependences between instructions in independent lifetimes of a fixed register so that instructions can be scheduled earlier than would otherwise be possible if those dependences were precisely honored.

Claims

1. An apparatus comprising:

at least one processor that includes at least one fixed register;

a memory coupled to the at least one processor;

a computer program residing in the memory that includes a selected instruction that defines at least one fixed register; and

an instruction scheduler residing in the memory and executed by the at least one processor, the instruction scheduler scheduling the selected instruction in a scheduling window, determining the lifetime in the scheduling window of the at least one fixed register defined in the selected instruction, and scheduling at least one other instruction within the lifetime of the at least one fixed register before scheduling any instruction that is in a different lifetime of the fixed register in the scheduling window.

2. The apparatus of claim 1 wherein the instruction scheduler builds a conditional dependence graph of a portion of the computer program and uses the information in the conditional dependence graph to schedule instructions in the selected portion.

3. The apparatus of claim 2 wherein the conditional dependence graph includes a conditional dependence between each instruction that begins an independent lifetime of the at least one fixed register and each previous instruction that defines the at least one fixed register.

4. The apparatus of claim 2 wherein the conditional dependence graph includes a conditional dependence between each instruction that begins an independent lifetime of the at least one fixed register and each previous instruction that uses the at least one fixed register.

5. The apparatus of claim 2 wherein the instruction scheduler schedules any instruction in the selected portion that has no dependences on other instructions in the conditional dependence graph, and wherein the instruction scheduler schedules any instruction in the selected portion that has only conditional dependences on other instrutions in the conditional dependence graph.

6. An apparatus comprising:

at least one processor that includes at least one fixed register;

a memory coupled to the at least one processor;

a computer program residing in the memory that includes a selected instruction within a scheduling window, wherein the selected instruction defines at least one fixed register;

means for scheduling the selected instruction in the scheduling window;

means for determining the lifetime in the scheduling window of the at least one fixed register defined in the selected instruction; and

means for scheduling at least one other instruction within the lifetime of the at least one fixed register before scheduling any instruction that is in a different lifetime of the fixed register in the scheduling window.

7. A method for scheduling a plurality of instructions within a scheduling window in a computer program, the method comprising the steps of:

scheduling a selected instruction in the scheduling window;

determining the lifetime in the scheduling window of at least one fixed register defined in the selected instruction, wherein the at least one fixed register comprises a physical register in a processor that executes the computer program; and

scheduling at least one other instruction within the lifetime of the at least one fixed register before scheduling any instruction that is in a different lifetime of the fixed register in the scheduling window.

8. The method of claim 7 wherein the step of scheduling the selected instruction includes the step of scheduling any instruction in the computer program that has no dependences on other instructions in the computer program, and scheduling any instruction that has only conditional dependences on other instructions in the computer program.

9. A method for scheduling a plurality of instructions in a computer program, the method comprising the steps of:

(A) building a conditional dependence graph from the plurality of instructions;

(B) seeding a ready list with at least one of the plurality of instructions based on the information in the conditional dependence graph;

(C) scheduling at least one instruction on the ready list;

(D) modifying the conditional dependence graph;

(E) updating the ready list from the modified conditional dependence graph;

(F) repeating steps (C) through (E) until the ready list is empty, signifying that all of the plurality of instructions have been scheduled.

10. The method of claim 9 wherein the step of building a conditional dependence graph includes the step of inserting at least one conditional dependence between an instruction that defines and begins an independent lifetime of a fixed register and previous instructions on which the instruction has a dependence due to definitions of the fixed register in the previous instructions.

11. The method of claim 9 wherein the step of building a conditional dependence graph includes the step of inserting at least one conditional dependence between an instruction that defines and begins an independent lifetime of a fixed register and previous instructions on which the instruction has a dependence due to uses of the fixed register in the previous instructions.

12. The method of claim 9 wherein the step of modifying the conditional dependence graph comprises the steps of:

for each instruction scheduled in step (C);

removing the instruction from the conditional dependence graph; and

removing dependences that point to the instruction.

13. The method of claim 9 wherein the step of seeding the ready list includes the step of placing on the ready list all instructions that:

have no dependences on other instructions in the conditional dependence graph; and

have only conditional dependences on other instructions in the conditional dependence graph.

14. A program product comprising:

(A) an instruction scheduler that schedules a selected instruction in a scheduling window of a computer program, determines the lifetime in the scheduling window of at least one fixed register defined in the selected instruction, wherein the at least one fixed register comprises a physical register in a processor that executes the computer program, and schedules at least one other instruction within the lifetime of the at least one fixed register before scheduling any instruction that is in a different lifetime of the fixed register in the scheduling window; and

(B) signal bearing media bearing the instruction scheduler.

15. The program product of claim 14 wherein the signal bearing media comprises recordable media.

16. The program product of claim 14 wherein the signal bearing media comprises transmission media.

17. The program product of claim 14 wherein the instruction scheduler builds a conditional dependence graph of a portion of the computer program and uses the information in the conditional dependence graph to schedule instructions in the selected portion.

18. The program product of claim 17 wherein the conditional dependence graph includes a conditional dependence between each instruction that begins an independent lifetime of the at least one fixed register and each previous instruction that defines the at least one fixed register.

19. The program product of claim 17 wherein the conditional dependence graph includes a conditional dependence between each instruction that begins an independent lifetime of the at least one fixed register and each previous instruction that uses the at least one fixed register.

20. The program product of claim 17 wherein the instruction scheduler schedules any instruction in the computer program that has no dependences on other instructions in the conditional dependence graph, and wherein the instruction scheduler schedules any instruction that has only conditional dependences on other instructions in the conditional dependence graph.