Power overlay chip scale packages for discrete power devices

• US 6,306,680 B1
• Filed: 02/22/1999
• Issued: 10/23/2001
• Est. Priority Date: 02/22/1999
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Fillion, Raymond Albert, Korman, Charles Steven, Esser, Albert Andreas Maria, Whitmore, Barry Scott
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LUU, CHUONG A
• Application Number:
  US09/255,412
• Time in Patent Office: 974 Days
• Field of Search: 438/107, 438/109, 438/110, 438/112, 438/121, 438/456, 438/612, 438/617, 438/106, 438/108, 438/124, 438/125, 438/126, 438/113
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/17106 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/2413 Connecting within a semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A power semiconductor device package includes at least one power semiconductor device mounted onto at least one electrically and thermally conductive spacer having an upper end surface bonded to a back surface of the device; a substrate of hardened substrate molding material surrounding the semiconductor device and the spacer except for an active major surface of the device and an lower end surface of the spacer, a dielectric film overlying the device active major surface and a top side of the substrate, the dielectric layer having a plurality of holes aligned with predetermined ones of the contact pads; a top side patterned metal layer on the dielectric film including portions extending into the holes electrically and thermally connected to contact pads of the device; and a backside metal layer on a substrate bottom side electrically and thermally connected to the spacer lower end surface. Optional through-post structures can be employed to bring all electrical connections either to the top side of the device package or the bottom side. Optional heat sinks can be mounted to the top side, the bottom side, or both sides.

Claims

1. A method of fabricating a power semiconductor device package comprising:

providing at least one power semiconductor device having an active major surface and an opposite major surface, with contact pads on the active major surface and a terminal contact on the opposite major surface;

providing a dielectric film having first and second sides, the dielectric film comprising a polymeric film;

forming holes through the dielectric film;

bonding the active major surface of the at least one power semiconductor device to the second side of the dielectric film, with the contact pads in alignment with the holes;

molding a dielectric encapsulant around the at least one semiconductor device on the second side of the dielectric film; and

forming a patterned electrically conductive layer on the first side of the dielectric film, portions of the patterned electrically conductive layer extending through the holes as vias into electrical contact with the device contact pads.

2. The method of claim 1, wherein molding the dielectric encapsulant around the at least one semiconductor device forms a device carrier;

and

the method further comprises mechanically sawing through the encapsulant and the dielectric film to define an extent of the package.

3. The method of claim 1, wherein bonding the major surface of the at least one power semiconductor device to the second side of the dielectric film comprises using an adhesive layer;

and wherein

the opposite major surface comprises a main terminal of the at least one power semiconductor device; and

which method further comprises, prior molding the dielectric encapsulant, bonding an electrically and thermally conductive spacer and the opposite major surface of the at least one power semiconductor device to each other.

4. The method of claim 3, which comprises bonding the spacer and the opposite major surface of the at least one power semiconductor device to each other prior to bonding the major surface of the at least one power semiconductor device to the second side of the dielectric film.

5. The method of claim 1, wherein:

further portions of the patterned electrically conductive layer on the first side of the dielectric film define package interconnect regions; and

which method further comprises;

forming a patterned solder mask over the patterned electrically conductive layer on the first side of the dielectric film, with openings in the solder mask defining areas for electrical connection to the package interconnect regions.

6. The method of claim 5, which further comprises applying solder to at least one of the package interconnect regions where exposed through one of the openings in the solder mask.

7. The method of claim 1, wherein bonding the active major surface of the at least one power semiconductor device to the second side of the dielectric film using an adhesive layer;

wherein

molding the dielectric encapsulant around the at least one semiconductor device forms a device carrier; and

wherein

the at least one power semiconductor device has a terminal contact on its opposite major surface; and

which method further comprises;

bonding an electrically and thermally conductive spacer and the opposite major surface of the at least one power semiconductor device to each other prior to molding a dielectric encapsulant,

mechanically grinding a surface opposite the dielectric film, and

subsequently mechanically sawing through the encapsulant and the dielectric film to define the extent of the package.

8. The method of claim 1, wherein bonding the active major surface of the at least one power semiconductor device to the second side of the dielectric film comprises using an adhesive layer;

and wherein

the opposite major surface comprises a main terminal of the at least one power semiconductor device; and

which method further comprises,

providing an electrically and thermally conductive interposer having a spacing portion configured to extend along the terminal contact on the opposite major surface of the at least one power semiconductor device, and a connection portion configured to extend generally parallel to a side surface of the at least one power semiconductor device to a termination surface, the termination surface positioned so as to be coplanar with the active major surface of the at least one power semiconductor device, and positioned so as to be in contact with the adhesive layer and in alignment with at least one of the holes when the at least one power semiconductor device is bonded to the dielectric film, and

bonding the connection portion of the interposer and the opposite major surface of the at least one power semiconductor device to each other.

9. The method of claim 1, which further comprises bonding an electrically conductive feed through element to the second side of the dielectric film, in alignment with at least one of the holes prior to molding the dielectric encapsulant.

10. The method of claim 9, wherein:

the opposite major surface comprises a main terminal of the at least one power semiconductor device; and

which further comprises;

electrically connecting the opposite major surface to the feed through element.

11. The method of claim 1, which further comprises bonding an electrically conductive feed through element in the form of an electrically conductive frame that encircles the at least one power semiconductor device to the second side of the dielectric film, in alignment with at least one of the holes prior to molding the dielectric encapsulant.

12. A method of fabricating a power semiconductor device package, comprising:

providing at least one power semiconductor device having an active major surface and an opposite major surface, with contact pads on the active major surface and a terminal contact on the opposite major surface;

bonding an electrically and thermally conductive spacer and the opposite major surface of the at least one power semiconductor device to each other;

providing a dielectric film having first and second sides and holes extending therethrough, the dielectric film comprising a polymeric film;

bonding the active major surface of the at least one power semiconductor device to the second side of the dielectric film, with the contact pads in alignment with the holes;

molding a dielectric encapsulant around the at least one semiconductor device and around at least portions of the spacer on the second side of the dielectric film to form a structure having a structure bottom opposite the dielectric film;

forming a patterned metal layer on the first side of the dielectric film, portions of the patterned metal layer extending through the holes into electrical contact with the device contact pads; and

grinding the structure from the structure bottom.

13. The method of claim 12 wherein grinding the structure from the structure bottom includes grinding the spacer.

14. A method of fabricating a power semiconductor device package, comprising:

providing a plurality of power semiconductor devices mounted onto electrically and thermally conductive spacers, each of the semiconductor devices having an active major surface and an opposite major surface, with contact pads on the active major surface and a terminal contact on the opposite major surface, the spacers being bonded to the opposite major surfaces of the devices;

providing a dielectric film having first and second sides and holes extending therethrough, the dielectric film comprising a polymeric film;

bonding the active major surfaces of the devices to the second side of the dielectric film, with the contact pads in alignment with the holes;

molding a dielectric encapsulant around the semiconductor devices and spacers on the second side of the dielectric film to form a structure having a structure bottom opposite the dielectric film;

grinding the structure from the structure bottom to expose the spacers and to provide a planar bottom surface;

forming a patterned metal layer on the first side of the dielectric film, portions of the patterned metal layer extending through the holes into electrical contact with the contact pads on the active major surfaces.

15. The method of claim 14, wherein providing the plurality of power semiconductor devices mounted onto electrically and thermally conductive spacers comprises:

attaching the devices to a plate of electrically and thermally conductive material, forming electrically and thermally conductive bonds between the device major surfaces and an upper surface of the plate; and

sawing the plate to define the spacers with mounted devices.

16. The method of claim 14, which further comprises:

providing at least one electrically conductive through-post;

bonding one end of the at least one electrically conductive through-post to the second side of the dielectric film prior to molding the dielectric encapsulant; and

wherein

during grinding the at least one through-post is exposed; and

a hole of the dielectric film and the one end of the at least one through-post are in alignment.

17. The method of claim 16, wherein

the patterned metal layer on the first side of the dielectric film provides thermal and electrical connections to the device contact pads and electrically connects the device contact pads to the at least one through-post;

and which further comprises;

providing a thermally conductive electrically insulating layer over the patterned metal layer on the first side of the dielectric film; and

mounting a heat sink to the thermally conductive electrically insulating layer.

18. The method of claim 14, wherein at least some of the power semiconductor devices are individually mounted onto separate spacers.

19. The method of claim 14, wherein at least some of the power semiconductor devices are mounted onto a common spacer.

20. The method of claim 14, which further comprises sawing through the structure between individual ones of the power semiconductor devices to produce a batch of single-device packages having thicknesses that match within a predetermined tolerance.

21. The method of claim 14, which further comprises:

providing a plurality of electrically conductive through-posts corresponding to individual ones of the plurality of power semiconductor devices;

bonding one end of each of the electrically conductive through-posts to the second side of the dielectric film adjacent to the corresponding one of the plurality of power semiconductor devices prior to molding the dielectric encapsulant; and

wherein

during grinding the through-posts are exposed; and

a respective hole and the one end of each of the through-posts are in alignment; and

which further comprises

sawing through the structure to produce a batch of single-device packages each including a power semiconductor device and a through-post, the packages having thicknesses that match within a predetermined tolerance.

22. The method of claim 14, which further comprises metallizing the bottom surface of the structure to provide thermal and electrical connections to the spacers.

23. The method of claim 14, which further comprises forming a patterned metal layer on the bottom surface of the structure to provide thermal and electrical connections to the spacers.

24. The method of claim 14, which further comprises soldering at least one metal plate to the spacers on the bottom surface of the structure.

25. The method of claim 14, which further comprises:

providing on the bottom surface of the structure a metal layer to provide thermal and electrical connections to the spacers and to electrically connect the spacers to the at least one through-post, and a thermally conductive electrically insulating layer over the metal layer; and

mounting a heat sink to the thermally conductive electrically insulating layer.

26. The method of claim 25, which further comprises coupling leads to the patterned metal layer on the first side of the dielectric film.