Method of forming a flip chip assembly, and a flip chip assembly formed by the method

• US 6,306,683 B1
• Filed: 03/16/2000
• Issued: 10/23/2001
• Est. Priority Date: 09/23/1997
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Questad, David L., Egitto, Frank D., Ouellet, Luc, Matienzo, Luis J., Ouellet, Charles, Tran, Son K., Rudik, William J., Dery, Jean
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Jones, Josetta I.
• Application Number:
  US09/526,569
• Time in Patent Office: 586 Days
• Field of Search: 438/108, 438/706
• US Class Current: 438/108
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: Y10S 438/959 : Mechanical polishing of wafer

Abstract

A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O₂ plasma or a microwave-generated Ar and N₂O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treat with the plasma before they are joined to one another. The plasma treatment improves adhesion between the encapsulant and the IC chip, and between the encapsulant and the chip carrier.

Claims

1. A method for forming a flip-chip on board assembly, comprising the steps of:

applying a plasma to chemically modify a surface of an insulation layer of an integrated circuit (IC) chip;

joining the IC chip to a chip carrier via a plurality of solder bumps electrically connecting a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier, such that a space is formed between the surface of the insulation layer and a surface of the chip carrier; and

applying an underfill encapsulant material to fill the space, wherein the step of applying the plasma is performed substantially without roughening the surface of the insulation layer.

2. The method according to claim 1, further comprising the step of mechanically roughening a surface of the chip carrier before the step of joining.

3. The method according to claim 2, further comprising the step of applying the plasma to a surface of the chip carrier after the step of mechanically roughening the surface of the chip carrier, but before the step of joining.

4. The method according to claim 2, wherein the step of applying the plasma is performed after the step of joining, and the surface of the chip carrier is also chemically modified.

5. The method according to claim 1, wherein the step of applying the plasma includes oxidizing the surface of the insulation layer.

6. The method according to claim 5, wherein the plasma is one of the group consisting of an O₂ plasma and a microwave-generated Ar and N₂O plasma.

7. The method according to claim 5, wherein the insulation layer is formed from a material that includes a hydrocarbon component.

8. The method according to claim 5, wherein the insulation layer consists of polyimide.

9. The method according to claim 5, wherein the chip carrier includes a laminate covered by the surface of the chip carrier, and the surface of the chip carrier comprises an epoxy resin with inorganic filler particles.

10. The method according to claim 1, wherein the step of applying the plasma includes the step of using a reactive ion etching system to treat the surface of the IC chip.

11. A method for forming a flip-chip assembly, said method comprising the steps of:

soldering a multiplicity of contact pads on a surface of said flip-chip to a respective multiplicity of contact pads on a surface of a chip carrier forming a space between said flip-chip surface and said chip carrier surface;

after the soldering step, plasma etching said flipchip surface and said chip carrier through said space; and

after the plasma etching step, applying an underfill material within said space to adhesively bond said flip-chip surface to said chip carrier surface.

12. A method as set forth in claim 11 wherein the plasma etching step improves the adhesion of said underfill material to said flip-chip surface.

13. A method as set forth in claim 12 wherein the plasma etching step improves the adhesion of said underfill material to said chip carrier surface.

14. A method as set forth in claim 11 wherein said chip carrier surface comprises organic material.

15. A method as set forth in claim 11 wherein said chip-carrier surface is formed by a passivation layer.

16. A method as set forth in claim 15 wherein said passivation layer comprises an organic material.

17. A method as set forth in claim 15 wherein said passivation layer comprises a layer of polyimide.

18. A method as set forth in claim 11 wherein said underfill material comprises a resin with an inorganic filler.

19. A method as set forth in claim 11 wherein said plasma etching is performed using oxygen plasma or microwave generated Ar and N2O plasma.

20. A method as set forth in claim 11 wherein said plasma etching step chemically modifies said flip-chip surface.

21. A method as set forth in claim 15 wherein said plasma etching step chemically modifies said passivation layer.

22. A method as set forth in claim 11 wherein said chip carrier surface comprises an organic layer with a filler material, and said plasma etching step exposes some of said filler material.

23. A method for forming a flip-chip assembly, said method comprising the steps of:

plasma etching a surface of said flip-chip, said plasma etching chemically modifying said surface of said flip-chip while causing less than 100 angstroms or roughening;

after the plasma etching step, soldering a multiplicity of contact pads on said surface of said flip-chip to a respective multiplicity of contact pads on a surface of a chip carrier forming a space between said flip-chip surface and said chip carrier surface; and

after the soldering step, applying an underfill material within said space to adhesively bond said flip-chip surface to said chip carrier surface.

24. A method as set forth in claim 23 wherein the plasma etching step improves the adhesion of said underfill material to said flip-chip surface.

25. A method as set forth in claim 23 further comprising the step of plasma etching said chip carrier surface before the soldering step.

26. A method as set forth in claim 25 wherein said chip carrier surface comprises an organic layer with an inorganic filler material, and said plasma etching step exposes some of said filler material.

27. A method as set forth in claim 26 wherein the plasma etching step improves the adhesion of said underfill material to said chip carrier surface due to the exposure of said filler material.

28. A method as set forth in claim 23 wherein said chip-carrier surface is formed by a passivation layer.

29. A method as set forth in claim 28 wherein said passivation layer comprises an organic material.

30. A method as set forth in claim 29 wherein said passivation layer comprises a layer of polyimide.

31. A method as set forth in claim 23 wherein said underfill material comprises a resin with an inorganic filler.

32. A method as set forth in claim 23 wherein said plasma etching is performed using oxygen plasma or microwave generated Ar and N2O plasma.

33. A method for forming a flip-chip assembly, said method comprising the steps of:

plasma etching a surface of a chip carrier, said chip carrier surface comprising an organic layer with an inorganic filler material, said plasma etching step exposing some of said filler material;

after the plasma etching step, soldering a multiplicity of contact pads on a surface of said flip-chip to a respective multiplicity of contact pads on said surface of said chip carrier forming a space between said flip-chip surface and said chip carrier surface; and

after the soldering step, applying an underfill material within said space to adhesively bond said flip-chip surface to said chip carrier surface.

34. A method as set forth in claim 33 wherein the plasma etching step improves the adhesion of said underfill material to said flip-chip surface.

35. A method as set forth in claim 33 wherein said underfill material comprises an organic material with an inorganic filler.

36. A method as set forth in claim 35 wherein said organic material of said underfill material is an epoxy resin.

37. A method as set forth in claim 33 further comprising the step of plasma etching said flip-chip surface before the soldering step.

38. A method as set forth in claim 37 wherein said chip-carrier surface is formed by a passivation layer.

39. A method as set forth in claim 38 wherein said passivation layer comprises an organic material.

40. A method as set forth in claim 39 wherein said passivation layer comprises a layer of polyimide.

41. A method as set forth in claim 33 wherein said plasma etching is performed using oxygen plasma or microwave generated Ar and N2O plasma.

42. A method as set forth in claim 33 wherein said organic material of said chip carrier surface comprises an epoxy resin.