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Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits

  • US 6,306,705 B1
  • Filed: 06/01/1999
  • Issued: 10/23/2001
  • Est. Priority Date: 07/03/1997
  • Status: Expired due to Term
First Claim
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1. A method of forming a DRAM array comprising the following steps:

  • defining a first node location, a second node location and a third node location;

    the second node location being electrically coupled to the first node location through a first transistor gate;

    the second node location being electrically coupled to the third node location through a second transistor gate;

    forming an electrically insulative layer over the node locations;

    removing portions of the electrically insulative layer to form a first opening, a second opening, and a third opening;

    the first, second and third openings extending to the first, second and third node locations, respectively;

    forming an undoped silicon layer within the first, second and third openings to narrow the first, second and third openings;

    forming a doped silicon layer within the narrowed openings;

    the undoped silicon layer and the doped silicon layer within the first opening together defining a first storage node;

    the undoped silicon layer and the doped silicon layer within the third opening together defining a second storage node;

    the undoped silicon layer and the doped silicon layer within the second opening together defining a conductive contact;

    removing a portion of the electrically insulative layer to expose sidewall surfaces of the first storage node, the second storage node and the conductive contact;

    forming rugged polysilicon on the exposed sidewall surfaces;

    forming a dielectric layer proximate the first and second storage nodes;

    forming a cell plate layer proximate the dielectric layer;

    the cell plate layer, dielectric layer and first storage node together defining a first capacitor;

    the cell plate layer, dielectric layer and second storage node together defining a second capacitor; and

    forming a bitline electrically connected to the conductive contact;

    the conductive contact and first capacitor together defining a first DRAM cell;

    the conductive contact and second capacitor together defining a second DRAM.

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