Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits

• US 6,306,705 B1
• Filed: 06/01/1999
• Issued: 10/23/2001
• Est. Priority Date: 07/03/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Parekh, Kunal R., Zahurak, John K., Wald, Phillip G.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US09/323,554
• Time in Patent Office: 875 Days
• Field of Search: 438/255, 438/398, 438/665, 438/674, 438/964, 438/FOR.189, 438/FOR.212, 438/FOR.488
• US Class Current: 438/255
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped nonrugged polysilicon.

Claims

1. A method of forming a DRAM array comprising the following steps:

defining a first node location, a second node location and a third node location;

the second node location being electrically coupled to the first node location through a first transistor gate;

the second node location being electrically coupled to the third node location through a second transistor gate;

forming an electrically insulative layer over the node locations;

removing portions of the electrically insulative layer to form a first opening, a second opening, and a third opening;

the first, second and third openings extending to the first, second and third node locations, respectively;

forming an undoped silicon layer within the first, second and third openings to narrow the first, second and third openings;

forming a doped silicon layer within the narrowed openings;

the undoped silicon layer and the doped silicon layer within the first opening together defining a first storage node;

the undoped silicon layer and the doped silicon layer within the third opening together defining a second storage node;

the undoped silicon layer and the doped silicon layer within the second opening together defining a conductive contact;

removing a portion of the electrically insulative layer to expose sidewall surfaces of the first storage node, the second storage node and the conductive contact;

forming rugged polysilicon on the exposed sidewall surfaces;

forming a dielectric layer proximate the first and second storage nodes;

forming a cell plate layer proximate the dielectric layer;

the cell plate layer, dielectric layer and first storage node together defining a first capacitor;

the cell plate layer, dielectric layer and second storage node together defining a second capacitor; and

forming a bitline electrically connected to the conductive contact;

the conductive contact and first capacitor together defining a first DRAM cell;

the conductive contact and second capacitor together defining a second DRAM.

2. The method of claim 1 wherein the exposed sidewall surfaces comprise undoped silicon, the method further comprising:

exposing a surface of the first storage node comprising the doped silicon layer;

exposing a surface of the second storage node comprising the doped silicon layer; and

substantially selectively forming HSG polysilicon from the exposed first and second storage node surfaces comprising undoped silicon and not from the exposed first and second storage node surfaces comprising doped silicon.

3. The method of claim 1 wherein the doped and undoped silicon layers are formed over the insulative layer, the method further comprising polishing the doped and undoped silicon layers to remove the doped and undoped silicon layers from over the electrically insulative layer.

4. A method of forming a DRAM array comprising the following steps:

defining a first node location, a second node location and a third node location;

the second node location being electrically coupled to the first node location through a first transistor gate;

the second node being electrically coupled to the third node location through a second transistor gate;

forming an electrically insulative layer over the node locations;

removing portions of the electrically insulative layer to form a first opening, a second opening, and a third opening;

the first, second and third openings extending to the first, second and third node locations, respectively;

forming an undoped silicon layer within the first, second and third openings to narrow the first, second and third openings;

forming a doped silicon layer within the narrowed first, second and third openings to further narrow the first, second and third openings;

forming a second undoped silicon layer within the further narrowed first, second and third openings;

the first undoped silicon layer, second undoped silicon layer and doped silicon layer within the first opening together defining a first storage node;

the first undoped silicon layer, second undoped silicon layer and doped silicon layer within the third opening together defining a second storage node;

the first undoped silicon layer, second undoped silicon layer and doped silicon layer within the second opening together defining a conductive contact;

removing a portion of the electrically insulative layer to expose sidewall surfaces of the first and second storage nodes and of the conductive contact;

forming rugged polysilicon on the exposed sidewall surfaces;

forming a dielectric layer proximate the first and second storage nodes;

forming a cell plate layer proximate the dielectric layer;

the cell plate layer, dielectric layer and first storage node together defining a first capacitor;

the cell plate layer, dielectric layer and second storage node together defining a second capacitor; and

forming a bitline electrically connected to the conductive contact;

the conductive contact and first capacitor together defining a first DRAM cell; and

the conductive contact and second capacitor together defining a second DRAM cell.

5. The method of claim 4 wherein the exposed sidewall surfaces comprise the first undoped silicon layer, the method further comprising:

exposing a surface of the first storage node comprising the second undoped silicon layer;

exposing a surface of the first storage node comprising the doped silicon layer;

exposing a surface of the second storage node comprising the second undoped silicon layer;

exposing a surface of the second storage node comprising the doped silicon layer; and

substantially selectively forming HSG polysilicon over the exposed first and second storage node surfaces comprising undoped silicon and not over the exposed first and second storage node surfaces comprising doped silicon.

6. The method of claim 4 wherein the doped and undoped silicon layers are formed over the insulative layer, the method further comprising polishing the doped and undoped silicon layers to remove the doped and undoped silicon layers from over the electrically insulative layer.