Method to form smaller channel with CMOS device by isotropic etching of the gate materials

• US 6,306,715 B1
• Filed: 01/08/2001
• Issued: 10/23/2001
• Est. Priority Date: 01/08/2001
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Chan, Lap, Pan, Yang, Quek, Elgin, Lee, James Yong Meng, Pradeep, Yelehanka Ramachandramurthy, Zheng, Jia Zhen, Leung, Ying Keung, Sundaresan, Ravi
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US09/756,008
• Time in Patent Office: 288 Days
• Field of Search: 257/344, 257/408, 257/411, 257/346, 257/336, 257/900, 257/369, 257/322, 438/303, 438/305, 438/586, 438/689, 438/713, 438/739, 438/307, 438/301, 438/595, 438/666
• US Class Current: 438/301
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method to form a MOS transistor with a narrow channel regions and a wide top (second) gate portion. A gate dielectic layer and a first gate layer are formed over a substrate. A second gate portion is formed over the first gate layer. Spacers are formed on the sidewalls of the second gate portion. In a critical step, we isotropically etch the first gate layer to undercut the second gate portion to form a first gate portion so that the first portion has a width less than the second gate portion. The spacers are removed. Lightly doped drains, sidewall spacers and source/drain regions are formed to complete the device.

Claims

1. A method of fabrication of CMOS transistor having a smaller channel;

comprising the steps of;

a) forming a gate dielectric layer over a substrate;

b) forming a first gate layer over said gate dielectric layer;

c) forming a second gate layer over said first gate layer;

d) patterning said second gate layer to form a second gate portion over said first gate layer;

e) forming spacers on the sidewalls of said second gate portion;

f) isotropically etching said first gate layer to undercut said second gate portion to form a first gate portion so that said first gate portion has a width less than said second gate portion;

g) removing said spacers;

h) forming lightly doped drains adjacent to said first gate portion and under said second gate portion;

i) forming sidewall spacers on the sidewalls of said first and second gate portions; and

j) forming source/drain regions adjacent to said sidewall spacers.

2. The method of claim 1 wherein said second gate layer and said first gate layer have a etch rate ratio of greater than 5:

1.

3. The method of claim 1 wherein said gate dielectric layer formed of a material selected from the group consisting of silicon oxide, tantalum oxide, silicon nitride, zirconium oxide, Hafnium oxide and titanium oxide.

4. The method of claim 1 wherein said a first gate layer has a thickness of between about 500 and 1000 Å

.

5. The method of claim 1 wherein said first gate layer is comprised of polysilicon and said second gate layer comprised of tungsten silicide.

6. The method of claim 1 wherein said second gate layer is comprised of Ta.

7. The method of claim 1 wherein said second gate layer is comprised of Ta, the first gate layer is comprised of TaN and the gate dielectric layer is comprised of Tantalum Oxide.

8. The method of claim 1 wherein said second gate layer having a thickness of between about 500 and 1000 Å

.

9. The method of claim 1 wherein said spacers are comprised of silicon oxide and have a thickness of between about 200 and 600 Å

.

10. The method of claim 1 wherein the isotropic etch comprises a Cl₂/O₂ etch chemistry or SF₆/Cl₂/O₂ etch chemistry.

11. The method of claim 1 wherein said first gate portion is narrower than said second gate portion by between about 10 to 20% of the width of the second gate portion.

12. The method of claim 1 wherein said a lightly doped drain formed using an angled ion implant so that the lightly doped drain is implanted under the second gate portion and said first gate portion.

13. A method of fabrication of CMOS transistor having a smaller channel, comprising the steps of:

a) forming a gate dielectric layer over a substrate;

b) gate dielectric layer formed of a material selected from the group consisting of silicon oxide, tantalum oxide, silicon nitride, zirconium oxide, Hafnium oxide and titanium oxide;

c) forming a first gate layer over said gate dielectric layer;

(1) said a first gate layer has a thickness of between about 500 and 1000 Å

;

(2) said first gate layer comprised of polysilicon, TiN or Ta;

d) forming a second gate layer over said first gate layer;

said second gate layer and said first gate layer have an etch rate ratio greater than 5;

1;

(1) said second gate layer comprised of W, Ta, or tungsten silicide;

(2) said second gate layer having a thickness of between about 500 and 1000 Å

;

e) forming a cap layer over said second gate layer;

said cap layer comprised of silicon oxide;

f) patterning said second gate layer and said cap layer to form a cap and a second gate portion over said first gate layer;

g) forming spacers on the sidewalls of said second gate portion;

(1) said spacers are comprised of silicon oxide and have a thickness of between about 200 and 600 Å

;

h) isotropically etching said first gate layer to undercut said second gate portion to form a first gate portion so that said first gate portion has a width less than said second gate portion;

(1) the isotropic etch comprising a Cl₂/O₂ etch chemistry or SF₆/Cl₂/O₂ etch chemistry;

(2) said first gate portion is narrower than said second gate portion by between about 10 to 20%;

i) removing said spacers;

j) forming lightly doped drains adjacent to said first gate portion and under said second gate portion;

(1) said lightly doped drains formed using an angled ion implant so that the lightly doped drain is implanted under the second gate portion and said first gate portion;

k) forming sidewall spacers on the sidewalls of said first and second gate portions; and

l) forming source/drain regions adjacent to said sidewall spacers.

14. The method of claim 13 which further includes forming silicide contacts to said source/drain regions and said second gate portion.