Method of patterning gate electrodes with high K gate dielectrics

• US 6,306,741 B1
• Filed: 07/13/2000
• Issued: 10/23/2001
• Est. Priority Date: 07/13/2000
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Li, Xia, Lee, James Yong Meng, Zhang, Yun Qiang
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): BERRY, RENEE R
• Application Number:
  US09/615,809
• Time in Patent Office: 467 Days
• Field of Search: 438/424, 438/426, 438/435, 438/585
• US Class Current: 438/585
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A buffer layer and a gate dielectric layer overlying a substrate having at least one active area is provided. A sacrificial oxide layer is formed over the gate dielectric layer. A nitride layer is formed over the sacrificial oxide layer. The nitride layer is patterned to form an opening therein within the active area exposing a portion of the sacrificial oxide layer within the opening. The portion of the sacrificial oxide layer within the opening is stripped, exposing a portion of the underlying gate dielectric layer within the opening. A gate electrode is formed within opening over the portion of the gate dielectric layer. The remaining nitride layer is selectively removed. The remaining sacrificial oxide layer is then stripped and removed.

Claims

1. A method of forming a gate electrode, comprising the following steps:

providing a silicon substrate having at least one active area;

a buffer layer overlies said silicon substrate and a gate dielectric layer overlies said buffer layer;

forming a sacrificial oxide layer over said gate dielectric layer;

forming a nitride layer over said sacrificial oxide layer;

patterning said nitride layer to form an opening therein within said active area exposing a portion of said sacrificial oxide layer within said opening;

stripping said portion of said sacrificial oxide layer within said opening exposing a portion of said underlying gate dielectric layer within said opening;

forming a gate electrode within said opening over said portion of said gate dielectric layer;

selectively removing said remaining nitride layer; and

stripping and removing said remaining sacrificial oxide layer.

2. The method of claim 1, wherein said nitride layer patterning step includes the steps of:

forming and patterning a layer of photoresist over said nitride layer to form a gate reverse mask; and

etching said nitride layer through said gate reverse mask to form said nitride layer opening within said active area.

3. The method of claim 1, wherein said buffer layer is from about 3 to 10 Å

thick;

said gate dielectric layer is from about 10 to 50 Å

thick;

said sacrificial oxide layer is from about 120 to 180 Å

thick; and

said nitride layer is from 2250 to 2750 Å

thick.

4. The method of claim 1, wherein said buffer layer is from about 3 to 10 Å

thick;

said gate dielectric layer is from about 20 to 25 Å

thick; and

said nitride layer is from 2400 to 2600 Å

thick.

5. The method of claim 1, wherein said gate dielectric layer is comprised of SiN;

and said buffer layer and said SiN gate dielectric layer are formed through Rapid Thermal Nitridation.

6. The method of claim 1, wherein said gate electrode formation step includes the steps of:

depositing a conductor layer over the structure filling said nitride layer opening and blanket filing said nitride layer;

chemically-mechanically polishing said conductor layer, removing the conductor layer over said nitride layer and forming said gate electrode.

7. The method of claim 1, wherein said select removal of said remaining nitride layer comprises an isotropic phosphoric acid wet etch of said remaining nitride layer.

8. The method of claim 1, wherein said select stripping of said remaining sacrificial oxide layer comprises an HF strip.

9. A method of forming a gate electrode, comprising the following steps:

providing a silicon substrate having at least one active area;

a buffer layer overlies said silicon substrate and a gate dielectric layer overlies said buffer layer;

said buffer layer being from about 3 to 10 Å

thick;

said gate dielectric layer being from about 10 to 50 Å

thick;

forming a sacrificial oxide layer over said gate dielectric layer;

forming a nitride layer over said sacrificial oxide layer;

said nitride layer being from about 2250 to 2750 Å

thick;

patterning said nitride layer to form an opening therein within said active area exposing a portion of said sacrificial oxide layer within said opening;

stripping said portion of said sacrificial oxide layer within said opening exposing a portion of said underlying gate dielectric layer within said opening;

forming a gate electrode within said opening over said portion of said gate dielectric layer;

selectively removing said remaining nitride layer; and

stripping and removing said remaining sacrificial oxide layer.

10. The method of claim 9, wherein said nitride layer patterning step includes the steps of:

forming and patterning a layer of photoresist over said nitride layer to form a gate reverse mask; and

etching said nitride layer through said gate reverse mask to form said nitride layer opening within said active area.

11. The method of claim 9, wherein said gate dielectric layer is from about 20 to 25 Å

thick; and

said nitride layer is from 2400 to 2600 Å

thick.

12. The method of claim 9, wherein said gate dielectric layer is comprised of SiN, and said buffer layer and said gate dielectric layer are formed through Rapid Thermal Nitridation.

13. The method of claim 9, wherein said gate electrode formation step includes the steps of:

depositing a conductor layer over the structure filling said nitride layer opening and blanket filing said nitride layer;

chemically-mechanically polishing said conductor layer, removing the conductor layer over said nitride layer and forming said gate electrode.

14. The method of claim 9, wherein said select removal of said remaining nitride layer comprises an isotropic phosphoric acid wet etch of said remaining nitride layer.

15. The method of claim 9, wherein said select stripping of said remaining sacrificial oxide layer comprises an HF strip.

16. The method of claim 9, wherein said buffer layer is comprised of a material selected from the group comprising SiO₂ and SiON;

said gate dielectric layer is comprised of a material selected from the group comprising SiN, Ta₃O₅, TiO₂, and Ta₂O₅; and

said gate electrode is comprised of a material selected from the group comprising polysilicon and a metal.

17. A method of forming a gate electrode, comprising the following steps:

providing a silicon substrate having at least one active area;

a buffer layer overlies said silicon substrate and a gate dielectric layer overlies said buffer layer;

said buffer layer being from about 3 to 10 Å

thick;

said gate dielectric layer being from about 10 to 50 Å

thick;

forming a sacrificial oxide layer over said gate dielectric layer;

forming a nitride layer over said sacrificial oxide layer;

said nitride layer being from about 2250 to 2750 Å

thick;

forming and patterning a layer of photoresist over said nitride layer to form a gate reverse mask;

etching said nitride layer through said gate reverse mask to form an opening therein within said active area exposing a portion of said sacrificial oxide layer within said opening;

stripping said portion of said sacrificial oxide layer within said opening exposing a portion of said underlying gate dielectric layer within said opening;

forming a gate electrode within said opening over said portion of said gate dielectric layer;

selectively removing said remaining nitride layer; and

stripping and removing said remaining sacrificial oxide layer.

18. The method of claim 17, wherein said gate dielectric layer is from about 20 to 25 Å

thick; and

said nitride layer is from 2400 to 2600 Å

thick.

19. The method of claim 17, wherein said gate dielectric layer is comprised of SiN, and said buffer layer and said gate dielectric layer are formed through Rapid Thermal Nitridation.

20. The method of claim 17, wherein said gate electrode formation step includes the steps of:

depositing a conductor layer over the structure filling said nitride layer opening and blanket filing said nitride layer;

chemically-mechanically polishing said conductor layer, removing the conductor layer over said nitride layer and forming said gate electrode.

21. The method of claim 17, wherein said select removal of said remaining nitride layer comprises an isotropic phosphoric acid wet etch of said remaining nitride layer.

22. The method of claim 17, wherein said select stripping of said remaining sacrificial oxide layer comprises an HF strip.

23. The method of claim 17, wherein said buffer layer is comprised of a material selected form the group comprising SiO₂ and SiON;

said gate dielectric layer is comprised of a material selected from the group comprising SiN, Ta₃O₅, TiO₂, and Ta₂O₅; and

said gate electrode is comprised of a material selected from the group comprising polysilicon and a metal.