Method for endpoint detection during dry etch of submicron features in a semiconductor device

• US 6,306,755 B1
• Filed: 05/14/1999
• Issued: 10/23/2001
• Est. Priority Date: 05/14/1999
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Zheng, Tammy
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, DUNG ANH
• Application Number:
  US09/312,730
• Time in Patent Office: 893 Days
• Field of Search: 438/631, 438/692, 438/693, 438/697, 438/707-709, 438/618, 438/633
• US Class Current: 438/631
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

According to an example embodiment, the present invention is directed to a method for manufacturing a semiconductor device. The device includes a conductive underlayer. A sub-micron via or contact path and a dummy via or dummy contact path are dry etched. The endpoint of the dry etching process is optically detected, and the etching process is stopped responsive to the detection of the endpoint. By etching a dummy via or contact in addition to the submicron via or contact, this example embodiment facilitates endpoint detection for dry etching sub-micron features in semiconductor devices, which is otherwise difficult or even impossible in the submicron regime.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming a conductive underlayer;

forming a selective layer over the conductive underlayer;

dry etching at least one sub-micron path;

concurrently dry etching at least one dummy path;

detecting the endpoint of the etching process; and

stopping the etching process responsive to the optical detection of the endpoint.

2. A method for manufacturing a semiconductor device, according to claim 1, wherein dry etching includes plasma etching.

3. A method for manufacturing a semiconductor device, according to claim 1, wherein the semiconductor device includes scribe lines, and wherein the dummy path is located at the scribe lines.

4. A method for manufacturing a semiconductor device, according to claim 1, wherein the semiconductor device includes at least one field area, and wherein the dummy path is located at a field area.

5. A method for manufacturing a semiconductor device, according to claim 1, further comprising:

patterning the conductive underlayer forming a dummy conductive metal; and

wherein detecting includes optically detecting.

6. A method for manufacturing a semiconductor device, according to claim 5, wherein the dummy path is located over the dummy conductive underlayer.

7. A method for manufacturing a semiconductor device, according to claim 1, further comprising:

patterning a field; and

forming a dummy field pattern.

8. A method for manufacturing a semiconductor device, according to claim 7, wherein the dummy path is located over the dummy field pattern.

9. A method for manufacturing a semiconductor device, according to claim 1, wherein the semiconductor device includes a total wafer area, and wherein the etched area of the dummy path and the sub-micron path is at least about 2% of the total wafer area.

10. A method for manufacturing a semiconductor device, according to claim 1, wherein the submicron paths are created for use as vias between the conductive underlayer and another conductive layer.

11. A method for manufacturing a semiconductor device, according to claim 10, further comprising forming metal into the submicron paths used as vias.

12. A method for manufacturing a semiconductor device, according to claim 1, wherein the submicron paths are created for use as contacts.

13. A method for manufacturing a semiconductor device, according to claim 12, further comprising:

forming at least one gate stack pattern, and

coupling at least one contact path to the gate stack region.

14. A method for manufacturing a semiconductor device, according to claim 12, further comprising:

forming at least one source region; and

coupling at least one contact path to a source region.

15. A method for manufacturing a semiconductor device, according to claim 12, further comprising:

forming at least one drain region; and

coupling at least one contact path to a drain region.

16. A method for manufacturing a semiconductor device, according to claim 12, wherein the dummy contact paths are coupled only to one type of underlayer.

17. A method for manufacturing a semiconductor device, according to claim 13, wherein at least one dummy gate stack pattern is added during a gate patterning step.

18. A method for manufacturing a semiconductor device, according to claim 17, wherein at least one dummy contact is located over a dummy gate stack pattern.

19. A method for manufacturing a semiconductor device, according to claim 12, further comprising forming metal in at least one contact path.