Complementary junction field effect transistors

• US 6,307,223 B1
• Filed: 12/09/1999
• Issued: 10/23/2001
• Est. Priority Date: 12/11/1998
• Status: Expired due to Term

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Lovoltech Incorporated
• Inventors: Yu, Ho-yuan
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/458,571
• Time in Patent Office: 684 Days
• Field of Search: 257/256, 257/263, 257/264, 257/266, 257/268, 257/272, 257/274, 257/277
• US Class Current: 257/256
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally “off” JFETs, one in N-channel and one in P-channel to form Complementary Junction Field Effect Transistors for high speed, low voltage and/or high current applications. The discrete device structure is disclosed in this invention. The integrated Complementary Junction Field Effect Transistors structure processed in standard CMOS process is disclosed in this invention. A vertical gate structure of Complementary Junction Field Effect Transistors is disclosed. Complementary Junction Field Effect Transistors structure is also disclosed in SOI substrate.

Claims

1. A complementary junction field effect transistor (JFET) circuit structure comprising:

an enhancement mode P-channel junction field effect transistor (JFET) having a Gate, Source and Drain; and

an enhancement mode N-channel junction field effect transistor (JFET) having a Gate, Source and Drain;

wherein one of either of the Drain or the Source of said enhancement mode P-channel JFET is electrically coupled to one of either of the Drain or the Source of said enhancement N-channel JFET and wherein the Gate of said enhancement mode P-channel JFET is electrically coupled to the Gate of said enhancement mode N-channel JFET.

2. The complementary JFET circuit structure of claim 1 wherein the Drain of the enhancement mode P-channel JFET is electrically coupled to the Drain of the enhancement mode N-channel JFET.

3. The complementary JFET circuit structure of claim 1 wherein the Source of the enhancement mode P-channel JFET is electrically coupled to the Drain of the enhancement mode N-channel JFET.

4. The complementary JFET circuit structure of claim 3 wherein the Source of the enhancement mode N-channel JFET is electrically coupled to a voltage source Vdd and the Drain of the enhancement mode P-channel JFET is electrically coupled to ground.

5. The complementary JFET circuit structure of claim 1 wherein the Drain of the enhancement mode P-channel JFET is electrically coupled to the Source of the enhancement mode N-channel JFET.

6. The complementary JFET circuit structure of claim 5 wherein the Source of the enhancement mode P-channel JFET is electrically coupled to a voltage source Vdd and the Drain of the enhancement mode N-channel JFET is electrically coupled to ground.

7. A complementary junction field effect transistor (JFET) circuit structure comprising:

an enhancement mode P-channel junction field effect transistor (JFET);

an enhancement mode N-channel junction field effect transistor (JFET);

wherein one of either of the Drain or the Source of said enhancement mode P-channel JFET is electrically coupled to one of either of the Drain or the Source of said enhancement N-channel JFET; and

wherein the Gate of said enhancement mode P-channel JFET is electrically coupled to the Gate of said enhancement mode N-channel JFET; and

wherein the Gate of the enhancement mode N-channel JFET comprises a plurality of electrically coupled gate elements separated by a distance W1, wherein each gate element is surrounded by a depletion region;

wherein the Gate of the enhancement mode P-channel JFET comprises a plurality of electrically coupled gate elements separated by a distance W2, wherein each gate element is surrounded by a depletion region;

wherein the threshold voltage for at least one of either the P-channel JFET or the N-channel JFET has been adjusted by increasing and decreasing the channel doping concentration near each depletion region surrounding each gate element and subsequently adjusting distances W1 and W2 by using an RTA thermal process.

8. The complementary JFET circuit structure of claim 7 wherein the Drain of the enhancement mode P-channel JFET is electrically coupled to the Drain of the enhancement mode N-channel JFET.

9. The complementary JFET circuit structure of claim 7 wherein the Source of the enhancement mode P-channel JFET is electrically coupled to the Drain of the enhancement mode N-channel JFET.

10. The complementary JFET circuit structure of claim 7 wherein the Drain of the enhancement mode P-channel JFET is electrically coupled to the Source of the enhancement mode N-channel JFET.

11. The complementary JFET circuit structure of claim 7 wherein the threshold voltage is between 0.2 and 0.3 volts.

12. The complementary JFET circuit structure of claim 7 wherein the enhancement mode P-channel JFET and the enhancement mode N-channel JFET are formed on a common semiconducting substrate.

13. The complementary JFET circuit structure of claim 12 wherein the enhancement mode P-channel JFET and the enhancement mode N-channel JFET are formed using a CMOS process.

14. The complementary JFET circuit structure of claim 12 wherein the common semiconducting substrate comprises an N+ type layer.

15. The complementary JFET circuit structure of claim 14 further comprising an N-epitaxial layer.

16. The complementary JFET circuit structure of claim 7 wherein the enhancement mode P-channel JFET and the enhancement mode N-channel JFET are formed on a common nonconducting substrate.

17. The complementary JFET circuit structure of claim 16 wherein the common nonconducting substrate consists of a dielectric material.

18. The complementary JFET circuit structure of claim 16 wherein the common nonconducting substrate comprises a semiconducting layer and a nonconducting layer.

19. The complementary JFET circuit structure of claim 16 wherein the enhancement mode P-channel JFET and the enhancement mode N-channel JFET are formed using an SOI process.

20. A method of fabricating a complementary JFET circuit structure comprising the steps of:

on a N-type substrate, forming a first plurality of gates for a N-channel JFET separated by a distance, W1, wherein each gate is surrounded by a depletion region;

forming a P-type well on said N-type substrate;

on said P-type well, forming a second plurality of gates for a P-channel JFET separated by a distance, W2, wherein each gate is surrounded by a depletion region;

adjusting a threshold voltage for said N-channel JFET and said P-channel JFET by increasing and decreasing channel doping concentration near each depletion region surrounding each gate wherein increasing said channel doping concentration near each depletion region decreases said threshold voltage; and

adjusting said threshold voltage by adjusting said distance W1 and said distance W2, using an RTA thermal process prior to metalization.

21. The product of the method of claim 20.

22. A method of fabricating a complementary JFET circuit structure comprising the steps of:

on a P-type substrate, forming a first plurality of gates for a P-channel JFET separated by a distance, W2, wherein each gate is surrounded by a depletion region;

forming a N-type well on said P-type substrate;

on said N-type well, forming a second plurality of gates for a N-channel JFET separated by a distance, W1, wherein each gate is surrounded by a depletion region;

adjusting a threshold voltage for said N-channel JFET and said P-channel JFET by increasing and decreasing channel doping concentration near each depletion region surrounding each gate wherein increasing said channel doping concentration near each depletion region decreases said threshold voltage; and

adjusting said threshold voltage by adjusting said distance W1 and said distance W2, using an RTA thermal process prior to metalization.

23. The product of the method of claim 22.