L-and U-gate devices for SOI/SOS applications

• US 6,307,237 B1
• Filed: 12/28/1999
• Issued: 10/23/2001
• Est. Priority Date: 12/28/1999
• Status: Expired due to Term

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Erstad, David Owen
• Primary Examiner(s): Ng&ocirc ; , Ng&acirc ;n V.
• Application Number:
  US09/473,158
• Time in Patent Office: 665 Days
• Field of Search: 257/204, 257/205, 257/206, 257/210, 257/353, 257/354, 257/401
• US Class Current: 257/401
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

A semiconductor device is disclosed that eliminates at least one of the channel/dielectric interfaces along the side walls of an SOI/SOS transistor channel, but does not require the use of a dedicated body tie contact. Because a dedicated body contact is not required, the packing density of the device may be significantly improved over conventional T-gate and H-gate configurations. The present invention may also reduce the overall gate area, which may increase both the speed and overall yield of the device.

Claims

1. A semiconductor device comprising:

active region formed on an insulating layer and surrounded by an isolation region, the active region having a top edge, a bottom edge, a first lateral edge, and a second lateral edge;

a first L-shaped gate having a first leg and a second leg;

the first leg of the first L-shaped gate spaced inward from the first lateral edge and spaced inward of the second lateral edge, and extending into the active region over the top edge;

the second leg of the first L-shaped gate spaced inward of the top edge and extending into the active region over the first lateral edge, the second leg of the first L-shaped gate intersecting the first leg of the first L-shaped gate but not extending to the second lateral edge;

a first drain region defined by the first lateral edge, the first leg of the first L-shaped gate, the top edge and the second leg of the first L-shaped gate;

a source region defined by the second lateral edge and the first L-shaped gate;

the source region and the drain region having a first conductivity type;

the active region under the first leg and the second leg of the first L-shaped gate having a second conductivity type;

a first implant region having the second conductivity type extending from a portion of the first L-shaped gate into at least a portion of the source region; and

a first electrically conducting layer extending over at least a portion of the first implant region and the source region for electrically connecting the first implant region to the source region.

2. A semiconductor device according to claim 1, wherein the second leg of the first L-shaped gate is spaced inward of the bottom edge.

3. A semiconductor device according to claim 1, wherein the second leg of the first L-shaped gate overlaps at least a portion of the bottom edge.

4. A semiconductor device according to claim 1, wherein the first leg of the first L-shaped gate extends over the bottom edge.

5. A semiconductor device according to claim 1, wherein the second leg of the first L-shaped gate extends past the first leg of the first L-shaped gate toward the second lateral edge, thereby forming a nub.

6. A semiconductor device according to claim 1, further comprising:

a second L-shaped gate having a first leg and a second leg;

the first leg of the second L-shaped gate spaced inward of the second lateral edge and spaced from the first L-shaped gate, the first leg of the second L-shaped gate extending into the active region over the top edge;

the second leg of the second L-shaped gate spaced inward from the top edge, and extending into the active region over the second lateral edge, the second leg of the second L-shaped gate intersecting the first leg of the second L-shaped gate but not extending to the first L-shaped gate;

a second drain region defined by the second lateral edge, the first leg of the second L-shaped gate, the top edge and the second leg of the second L-shaped gate;

the source region extending between the second L-shaped gate and the first L-shaped gate;

the active region under the first leg and the second leg of the second L-shaped gate having the second conductivity type;

a second implant region having the second conductivity type extending from a portion of the second L-shaped gate into at least a portion of the source region; and

a second electrically conducting layer extending over at least a portion of the second implant region and the source region for electrically connecting the second implant region to the source region.

7. A semiconductor device according to claim 6, wherein the first implant region and the second implant region are a common implant region.

8. A semiconductor device according to claim 6, wherein the first electrically conducting layer and the second electrically conducting layer are a common electrically conducting layer.

9. A semiconductor device according to claim 8, wherein the first electrically conducting layer and the second electrically conducting layer are formed from a silicide layer.

10. A semiconductor device according to claim 6, wherein the second leg of the second L-shaped gate is spaced inward from the bottom edge.

11. A semiconductor device according to claim 6, wherein the second leg of the second L-shaped gate overlaps at least a portion of the bottom edge.

12. A semiconductor device according to claim 6, wherein the first leg of the second L-shaped gate also extends over the bottom edge.

13. A semiconductor device according to claim 6, wherein the second leg of the second L-shaped gate extends past the first leg of the second L-shaped gate toward the first lateral edge, thereby forming a nub.

14. A semiconductor device comprising:

an active region formed on an insulating layer and surrounded by an isolation region, the active region having a top edge, a bottom edge, a first lateral edge, and a second lateral edge;

a first U-shaped gate having a first leg, a second leg and a third leg;

the first leg of the first U-shaped gate spaced inward from the first lateral edge and inward of the second lateral edge;

the second leg of the first U-shaped gate extending into the active region over the first lateral edge, the second leg of the first U-shaped gate intersecting the first leg of the first U-shaped gate but not extending to the second lateral edge;

the third leg of the first U-shaped gate spaced from the second leg of the first U-shaped gate, the third leg of the first U-shaped gate extending into the active region over the first lateral edge and intersecting the first leg of the first U-shaped gate but not extending to the second lateral edge;

a first drain region defined by the first lateral edge, the first leg of the first U-shaped gate, the second leg of the first U-shaped gate and the third leg of the first U-shaped gate;

a source region defined by the second lateral edge and the first U-shaped gate;

the source region and the drain region having a first conductivity type;

the active region under the first leg, the second leg and the third leg of the first U-shaped gate having a second conductivity type;

a first implant region having the second conductivity type extending from a portion of the first U-shaped gate into at least a portion of the source region; and

a first electrically conducting layer extending over at least a portion of the first implant region and the source region for electrically connecting the first implant region to the source region.

15. A semiconductor device according to claim 14, wherein the second leg of the first U-shaped gate is spaced inward of the top edge.

16. A semiconductor device according to claim 14, wherein the second leg of the first U-shaped gate overlaps at least a portion of the top edge.

17. A semiconductor device according to claim 14, wherein the third leg of the first U-shaped gate is spaced inward of the bottom edge.

18. A semiconductor device according to claim 14, wherein the third leg of the first U-shaped gate overlaps at least a portion of the bottom edge.

19. A semiconductor device according to claim 14, wherein the first leg of the first U-shaped gate extends over the bottom edge.

20. A semiconductor device according to claim 14, wherein the first leg of the first U-shaped gate extends over the top edge.

21. A semiconductor device according to claim 14, wherein the second leg of the first U-shaped gate extends past the first leg of the first U-shaped gate toward the second lateral edge, thereby forming a first nub.

22. A semiconductor device according to claim 14, wherein the third leg of the first U-shaped gate extends past the first leg of the first U-shaped gate toward the second lateral edge, thereby forming a second nub.

23. A semiconductor device according to claim 14, further comprising:

a second U-shaped gate having a first leg, a second leg and a third leg;

the first leg of the second U-shaped gate spaced inward of the second lateral edge and spaced from the first U-shaped gate;

the second leg of the second U-shaped gate extending into the active region over the second lateral edge, the second leg of the second U-shaped gate intersecting the first leg of the second U-shaped gate but not extending to the first U-shaped gate;

the third leg of the second U-shaped gate spaced from the second leg of the second U-shaped gate and extending into the active region over the second lateral edge, the third leg of the second U-shaped gate intersecting the first leg of the second U-shaped gate but not extending to the first U-shaped gate;

a second drain region defined by the first second edge, the first leg of the second U-shaped gate, the second leg of the second U-shaped gate and the third leg of the second U-shaped gate;

the source region defined by the space between the first U-shaped gate and the second U-shaped gate;

the active region under the first leg, the second leg and the third leg of the second U-shaped gate having the second conductivity type;

a second implant region extending from a portion of the second U-shaped gate into at least a portion of the source region; and

a second electrically conducting layer extending over at least a portion of the second implant region and the source region for electrically connecting the second implant region to the source region.

24. A semiconductor device according to claim 23, wherein the first implant region and the second implant region are a common implant region.

25. A semiconductor device according to claim 24, wherein the first electrically conducting layer and the second electrically conducting layer are a common electrically conducting layer.

26. A semiconductor device according to claim 25, wherein the first electrically conducting layer and the second electrically conducting layer are formed from a silicide layer.

27. A semiconductor device according to claim 23, wherein the second leg of the second U-shaped gate is spaced inward of the top edge.

28. A semiconductor device according to claim 23, wherein the second leg of the second U-shaped gate overlaps at least a portion of the top edge.

29. A semiconductor device according to claim 23, wherein the third leg of the second U-shaped gate is spaced inward of the bottom edge.

30. A semiconductor device according to claim 23, wherein the third leg of the second U-shaped gate overlaps at least a portion of the bottom edge.

31. A semiconductor device according to claim 23, wherein the first leg of the second U-shaped gate extends over the bottom edge.

32. A semiconductor device according to claim 23, wherein the first leg of the second U-shaped gate extends over the top edge.

33. A semiconductor device according to claim 23, wherein the second leg of the second U-shaped gate extends past the first leg of the second U-shaped gate toward the first lateral edge, thereby forming a third nub.

34. A semiconductor device according to claim 33, wherein the third leg of the second U-shaped gate extends past the first leg of the second U-shaped gate toward the first lateral edge, thereby forming a fourth nub.

35. A semiconductor device according to claim 23, wherein the first, second and third legs of the first U-shaped gate are integrally formed.

36. A semiconductor device according to claim 35, wherein the first, second and third legs of the second U-shaped gate arc integrally formed.