Semiconductor resurf devices formed by oblique trench implantation

• US 6,307,246 B1
• Filed: 03/20/2000
• Issued: 10/23/2001
• Est. Priority Date: 07/23/1998
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Uenisi, Akio, Nitta, Tetsuya, Minato, Tadaharu
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): PERT, EVAN T
• Application Number:
  US09/508,896
• Time in Patent Office: 582 Days
• Field of Search: 438/268, 438/270, 438/294, 438/296, 438/299, 438/302, 438/525, 257/213, 257/288, 257/327, 257/328, 257/329, 257/330, 257/334, 257/335, 257/336, 257/337, 257/339, 257/365, 257/401, 257/408, 257/409, 257/476, 257/493, 257/491, 257/492
• US Class Current: 257/493
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor substrate has a first main surface with a plurality of trenches 5a sandwiching a region in which p and n diffusions regions 2 and 3 are formed to provide a p-n junction along the depth of the trenches. P diffusion region 2 has a doping concentration profile provided by a p dopant diffused from a sidewall surface of one trench 5a, and n diffusion region 3 has a doping concentration profile provided by an n dopant diffused from a sidewall surface of the other trench 5a. A heavily doped n⁺ substrate region 1 is provided at a second main surface side of p and n diffusion regions 2 and 3. A depth Ld of trench 5a from the first main surface is greater than a depth Nd of p and n diffusion regions 2, 3 from the first main surface by at least a diffusion length L of the p dopant in p diffusion region 2 or the n dopant in n diffusion region 3 in manufacturing the semiconductor device. A high withstand voltage and low ON-resistance semiconductor device can thus be obtained.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type, having first and second main surfaces opposite to each other, said first main surface being provided with a plurality of trenches,

a first doped region of the first conductivity type formed in a mesa region of said semiconductor substrate between an adjacent pair of said plurality of trenches at a sidewall surface of one trench of said pair, having a doping concentration profile provided by a dopant of the first conductivity type diffused from the sidewall surface of said one trench, and having a doping concentration lower than that of a region of the first conductivity type of said semiconductor substrate, and

a second doped region of a second conductivity type formed in said mesa region at a sidewall surface opposite to the sidewall surface of said one trench, having a doping concentration profile provided by a dopant of the second conductivity type diffused from the sidewall surface opposite to the sidewall surface of said one trench, and forming a p-n junction together with said first doped region, said p-n junction located along the depth direction of said plurality of trenches,

said adjacent pair of trenches having a first extending portion extending from said main surface to a first depth position while having a sidewall surface with a predetermined inclination maintained with respect to said first main surface,

said first and second doped regions being shallower than said first depth position, as measured from said first main surface, by at least a length of diffusion of said dopants of the first and second conductivity types in manufacturing the semiconductor device.

2. The semiconductor device according to claim 1, wherein said adjacent pair of trenches each also have a second extending portion tapering toward said second main surface, said second extending portion extending deeper than said first depth position towards said second main surface to a second depth position and having a sidewall surface with an inclination different from that of said first extending portion.

3. The semiconductor device according to claim 1, further comprising:

a third doped region of the second conductivity type formed at said first main surface side of said first and second doped regions and electrically connected to said second doped region;

a fourth doped region of the first conductivity type formed at at least one of said first main surface or a sidewall surface of said one trench such that said fourth doped region is opposite to said first doped region with said third doped region posed therebetween; and

a gate electrode layer opposite to said third doped region between said first and fourth doped regions, with a gate insulation layer interposed therebetween.

4. The semiconductor device according to claim 3, wherein said gate electrode layer is provided in at least of said trenches.

5. The semiconductor device according to claim 3, wherein said gate electrode layer is formed on said first main surface.

6. The semiconductor device according to claim 1, further comprising a third doped region of the second conductivity type formed at said first main surface side of said first and second dope regions and electrically connected to said second doped region.

7. The semiconductor device according to claim 1, further comprising an electrode layer in Schottky contact with said first doped region.

8. The semiconductor device according to claim 1, wherein a diffusion length of each of said dopants of the first and second conductivity types in manufacturing the semiconductor device is longer than a distance from the sidewall surfaces of said adjacent pair of trenches to said p-n junction of said first and second doped regions.

9. A method of manufacturing a semiconductor device comprising the steps of:

providing a semiconductor substrate having first and second main surfaces opposite to each other, said semiconductor substrate having a heavily doped region of a first conductivity type at said second main surface and having a lightly doped region of the first conductivity type at said first main surface side,

providing in said semiconductor substrate a plurality of trenches having a first extending portion extending from said first main surface into said heavily doped region to a first depth position while having a sidewall surface with a predetermined inclination maintained relative to said first main surface,

obliquely implanting a dopant of the first conductivity type in a mesa region of said semiconductor substrate between an adjacent pair of said plurality of trenches at a sidewall surface of one trench, to form at the sidewall surface of said one trench a first doped region of the first conductivity type having a doping concentration lower than that of said heavily doped region, and

obliquely implanting a dopant of the second conductivity type in said mesa region at a sidewall surface opposite to the sidewall implanted with said dopant of the first conductivity type, to provide a second doped region of the second conductivity type at the sidewall surface opposite to the sidewall implanted with said dopant of the first conductivity type, to provide a p-n junction of the first and second doped regions located along the depth direction of said plurality of trenches,

said first depth position being closer to said second main surface than a junction of said heavily and lightly doped regions to said second main surface by at least a diffusion length of each of said dopants of the first and second conductivity types in manufacturing the semiconductor device,

said dopants of the first and second conductivity types being each implanted at an angle allowing each of said dopants of the first and second conductivity types to be directly introduced into a sidewall surface of said treches located at a depth closer to said second main surface than said junction of said heavily and lightly doped regions to said second main surface by at least said diffusion length of each of said dopants of the first and second conductivity types in manufacturing the semiconductor device.

10. The method according to claim 9, wherein said plurality of trenches each have a second extending portion tapering toward said second main surface, said second extending portion extending deeper than said first depth position towards said second main surface to a second depth position while having a sidewall surface with an inclination different from that of said first extending portion.

11. The method according to claim 9, further comprising:

providing a third doped region of the second conductivity type at said first main surface side of said first and second doped regions to be electrically connected to said second doped region;

providing a fourth doped region of the first conductivity type at at least one of said first main surface or a sidewall surface of said one trench such that said fourth doped region is opposite to said first doped region with said third doped region posed therebetween; and

providing a gate electrode layer opposite to said third doped region between said first and fourth doped regions, with a gate insulation layer interposed therebetween.

12. The method according to claim 11, wherein said gate electrode layer is formed in at least one of said trenches.

13. The method according to claim 11, wherein said gate electrode layer is formed on said first main surface.

14. The method according to claim 9, further comprising the step of providing a third doped region of the second conductivity type at said first main surface side of said first and second doped regions to be electrically connected to said second doped region.

15. The method according to claim 9, further comprising the step of providing an electrode layer in Schottky contact with said first doped region.

16. The method according to claim 9, wherein a diffusion length of each of said dopants of the fast and second conductivity types in manufacturing the semiconductor device is longer than a distance from the sidewall surfaces of said adjacent pair of trenches to said p-n junction of said first and second doped regions.