Gate driver circuit for high and low side switches with primary and secondary shoot-through protection

• US 6,307,409 B1
• Filed: 12/08/2000
• Issued: 10/23/2001
• Est. Priority Date: 12/08/2000
• Status: Expired due to Term

• Current Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Original Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Inventors: Wrathall, Robert S.
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US09/733,317
• Time in Patent Office: 319 Days
• Field of Search: 327/112, 327/108, 327/110, 327/111, 327/374, 327/376, 327/377, 326/22, 326/23, 326/26, 326/27, 326/82, 326/83, 326/86, 326/87
• US Class Current: 327/112
• CPC Class Codes: H03K 17/08122 in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors

Abstract

A driver circuit for alternately driving a first transistor and a second transistor connected in series includes primary and secondary anti-shoot-through protection. The driver circuit prevents shoot-through at the first and second transistors by using a pair of switch lock-out signals. The switch lock-out signals prevent one transistor from turning on until the other transistor is turned off. The driver circuit eliminates shoot-through in the driver devices driving the first and second transistors by using a pair of driver lock-out signals. The driver devices are turned on only briefly during the transitions of the first and second transistors. Otherwise, the driver devices are turned off. The driver lock-out signals ensure that no contention occurs between the driver devices and furthermore, set up the driver devices for the next On-Off switching sequence. The driver circuit can achieve a fast switching operation as well as improve the efficiency of the power transistors.

Claims

1. A driver circuit for alternately driving a first transistor and a second transistor in response to a switch control signal, said first and second transistors being connected in series between a first power supply and a second power supply and generating an output voltage at an output node for driving a load, comprising:

a first driver circuit portion for driving a control terminal of said first transistor in response to said switch control signal, said first driver circuit portion comprising;

a first control path for generating a turn-on signal for turning on said first transistor;

a second control path for generating a turn-off signal for turning off said first transistor; and

a third control path for generating a holding signal for holding an on or off state of said control terminal of said first transistor, said third control path having a drive capability less than a drive capability of said first control path or said second control path;

wherein said first control path enables said turn-on signal and said third control path enables said hold signal only after said second transistor is turned off;

said first control path disables said turn-on signal and said second control path disables said turn-off signal when said control terminal of said first transistor has moved to a respective on or off state; and

said holding signal of said third control path holds said on-off state of said control terminal of said first transistor when said turn-on signal or said turn-off signal is disabled.

2. The driver circuit of claim 1, further comprising:

a second driver circuit portion for driving a control terminal of said second transistor in response to said switch control signal, said second driver circuit portion comprising;

a fourth control path for generating a turn-on signal for turning on said second transistor;

a fifth control path for generating a turn-off signal for turning off said second transistor; and

a sixth control path for generating a holding signal for holding an on or off state of said control terminal of said second transistor, said sixth control path having a drive capability less than a drive capability of said fourth control path or said fifth control path;

wherein said fourth control path enables said turn-on signal and said sixth control path enables said hold signal only after said first transistor is turned off;

said fourth control path disables said turn-on signal and said fifth control path disables said turn-off signal when said control terminal of said second transistor has moved to a respective on or off state; and

said holding signal of said sixth control path holds said on-off state of said control terminal of said second transistor when said turn-on signal or said turn-off signal is disabled.

3. The driver circuit of claim 1, wherein:

said first control path comprises a first logic circuit for providing an OR function, a first amplifier, and a first driver device connected in series;

said second control path comprises a second logic circuit for providing an AND function, a second amplifier, and a second driver device connected in series;

said first driver device and said second driver device are connected in series between said first power supply and said second power supply, and an output node between said first driver device and said second driver device is coupled to said control terminal of said respective one of said first transistor or second transistor;

said third control path comprises an inverter; and

a third logic circuit coupled to said first, second and third control paths, said third logic circuit generating an output signal in response to said switch control signal and a switch lock-out signal indicative of an on-off status of an opposite one of said first or second transistor.

4. A driver circuit for alternately driving a first transistor and a second transistor in response to a switch control signal, said first transistor being connected in series with a second transistor between a first power supply and a second power supply, comprising:

a first driver circuit portion for driving a control terminal of said first transistor in response to said switch control signal, said first driver circuit portion comprising;

a first driver device and a second driver device connected in series between said first power supply and said second power supply, said first and second driver devices generating a control signal at an output node between said first and second driver devices, said control signal being coupled to said control terminal of said first transistor for controlling an on-off state of said first transistor;

a first logic circuit having a first input terminal coupled to receive said switch control signal, a second input terminal coupled to receive a first lock-out signal, and an output terminal, said first lock-out signal indicating an on-off status of said second transistor, and said switch control signal having a first state for turning said first transistor on and turning said second transistor off, and a second state for turning said second transistor on and turning said first transistor off;

a second logic circuit for providing an OR function having a first input terminal coupled to said output terminal of said first logic circuit, a second input terminal coupled to receive a second lock-out signal, and an output terminal;

a first amplifier having an input terminal coupled to said output terminal of said second logic circuit and generating an output signal for driving said first driver device;

a third logic circuit for providing an AND function having a first input terminal coupled to said output terminal of said first logic circuit, a second input terminal coupled to receive said second lock-out signal, and an output terminal;

a second amplifier having an input terminal coupled to said output terminal of said third logic circuit and generating an output signal for driving said second driver device;

a first inverter having an input terminal coupled to said output terminal of first logic circuit and an output terminal coupled to said output node of said first and second driver devices, said output terminal generating a third lock-out signal for said second transistor; and

a delay element coupled to said output node of said first and second driver devices and generating said second lock-out signal.

5. The driver circuit of claim 4, wherein when said switch control signal changes from said second state to said first state, said first logic circuit delays said first transistor from turning on until said first lock-out signal indicates that said second transistor is turned off.

6. The driver circuit of claim 4, wherein said first logic circuit provides a NOR function when said first transistor is to be turned on when said switch control signal has a low logic level.

7. The driver circuit of claim 6, wherein said first transistor is a PMOS transistor.

8. The driver circuit of claim 6, wherein said first transistor is an NMOS transistor and said circuit further comprises:

an inverter coupled to said output node of said first and second driver devices for inverting a logic state of said control signal for said first transistor.

9. The driver circuit of claim 4, wherein said first logic circuit provides a NAND function when said first transistor is to be turned on when said switch control signal has a high logic level.

10. The driver circuit of claim 9, wherein said first transistor is an NMOS transistor.

11. The driver circuit of claim 9, wherein said first transistor is a PMOS transistor and said circuit further comprises:

an inverter coupled to said output node of said first and second driver devices for inverting a logic state of said control signal for said first transistor.

12. The driver circuit of claim 4, wherein said first inverter comprises a plurality of inverters connected in series, said plurality of inverters having increasing drive capability between a first one and a last one of said plurality of inverters.

13. The driver circuit of claim 4, wherein said first inverter comprises a CMOS inverter.

14. The driver circuit of claim 4, wherein said first inverter comprises a bipolar inverter.

15. The driver circuit of claim 4, wherein said second logic circuit is an OR gate.

16. The driver circuit of claim 4, wherein said second logic circuit is an NOR gate and said first amplifier is an inverting amplifier.

17. The driver circuit of claim 16, wherein said inverting amplifier comprises a plurality of inverters connected in series, said plurality of inverters having increasing drive capability between a first one and a last one of said plurality of inverters.

18. The driver circuit of claim 4, wherein said third logic circuit is an AND gate.

19. The driver circuit of claim 4, wherein said third logic circuit is an NAND gate and said second amplifier is an inverting amplifier.

20. The driver circuit of claim 18, wherein said inverting amplifier comprises a plurality of inverters connected in series, said plurality of inverters having increasing drive capability between a first one and a last one of said plurality of inverters.

21. The driver circuit of claim 4, wherein said first and second driver devices are MOS transistors.

22. The driver circuit of claim 21, wherein said first driver device is a PMOS transistor and said second driver device is an NMOS transistor.

23. The driver circuit of claim 4, wherein said first and second driver devices are bipolar transistors.

24. The driver circuit of claim 23, wherein said first driver device is a PNP transistor and said second driver device is an NPN transistor.

25. The driver circuit of claim 4, wherein said first transistor and said second transistor are MOS transistors.

26. The driver circuit of claim 4, wherein said first transistor and said second transistor are bipolar transistors.

27. The driver circuit of claim 4, wherein said driver circuit is fabricated as an integrated circuit.

28. The driver circuit of claim 27, wherein said driver circuit and said first and second transistors are fabricated on the same integrated circuit.

29. The driver circuit of claim 4, wherein said first power supply is a positive power supply.

30. The driver circuit of claim 4, wherein said second power supply is ground or a negative power supply.

31. The driver circuit of claim 4, wherein said first inverter has a drive capability less than a drive capability of said first or second driver device.

32. The driver circuit of claim 4, further comprising:

a second driver circuit portion for driving a control terminal of said second transistor in response to said switch control signal, said second driver circuit portion comprising;

a third driver device and a fourth driver device connected in series between said first power supply and said second power supply, said third and fourth driver devices generating a control signal at an output node between said third and fourth driver devices, said control signal being coupled to said control terminal of said second transistor for controlling an on-off state of said second transistor;

a fourth logic circuit having a first input terminal coupled to receive said switch control signal, a second input terminal coupled to receive said third lock-out signal, and an output terminal, said third lock-out signal indicating an on-off status of said first transistor;

a fifth logic circuit for providing an OR function having a first input terminal coupled to said output terminal of said fourth logic circuit, a second input terminal coupled to receive a fourth lock-out signal, and an output terminal;

a third amplifier having an input terminal coupled to said output terminal of said fifth logic circuit and generating an output signal for driving said third driver device;

a sixth logic circuit for providing an NAND function having a first input terminal coupled to said output terminal of said fourth logic circuit, a second input terminal coupled to receive said fourth lock-out signal, and an output terminal;

a fourth amplifier having an input terminal coupled to said output terminal of said sixth logic circuit and generating an output signal for driving said fourth driver device;

a second inverter having an input terminal coupled to said output terminal of fourth logic circuit and an output terminal coupled to said output node of said third and fourth driver devices, said output terminal generating said first lock-out signal for said first transistor; and

a second delay element coupled to said output node of said third and fourth driver devices and generating said fourth feedback signal.

33. The driver circuit of claim 32, wherein said first transistor is a NMOS transistor and said second transistor is a PMOS transistor.

34. The driver circuit of claim 32, wherein said first and third driver devices are PMOS transistors and said second and fourth driver devices are NMOS transistors.

35. The driver circuit of claim 32, wherein said fifth logic circuit is a NOR gate, said sixth logic circuit is a NAND gate, and said third and fourth amplifiers are each an inverting amplifier.

36. A method for alternately driving a first transistor and a second transistor connected in series in response to a switch control signal, comprising:

generating a first lock-out signal indicating an on-off status of said first transistor, wherein said first lock-out signal transitions a first delay time after a transition said switch control signal;

preventing said second transistor from turning on when said first lock-out signal indicates said first transistor is turned on;

turning off said first transistor in response to a transition of said switch control signal; and

turning on said second transistor when said first lock-out signal indicates said first transistor is turned off, said turning on comprising;

driving a control terminal of said second transistor to a first voltage level using a first driver device, thereby turning on said second transistor;

turning off said first driver device after said second transistor is turned on; and

driving said control terminal of said second transistor using a first holding device.

37. The method of claim 36, wherein said first driver device is a MOS transistor having a large drive capability and said first holding device is a MOS transistor having a drive capability less than said first driver device.

38. The method of claim 36, wherein said first voltage level is substantially equal to a logic threshold level.

39. The method of claim 36, wherein said turning off said first transistor comprises:

driving said control terminal of said first transistor to a second voltage level using a second driver device, thereby turning off said first transistor;

turning off said second driver device after said first transistor is turned off; and

driving said control terminal of said first transistor using a second holding device.

40. The method of claim 39, wherein said second voltage level is substantially equal to a logic threshold level.

41. The method of claim 39, wherein said second driver device is a MOS transistor having a large drive capability and said second holding device is a MOS transistor having a drive capability less than said second driver device.

42. A method for driving a first transistor, connect in series with a second transistor, in response to a switch control signal, comprising:

turning on said first transistor in response to said switch control signal, said turning on comprising;

driving a control terminal of said first transistor to a first voltage level using a first driver device, thereby turning on said first transistor;

turning off said first driver device after said first transistor is turned on; and

driving said control terminal of said first transistor using a first holding device.

43. The method of claim 42, further comprising:

turning off said first transistor in response to said switch control signal, said turning off comprising;

driving said control terminal of said first transistor to a second voltage level using a second driver device, thereby turning off said first transistor;

turning off said second driver device after said first transistor is turned off; and

driving said control terminal of said first transistor using said first holding device.

44. The method of claim 42, wherein said first voltage level is substantially equal to a logic threshold level.

45. The method of claim 43, wherein said first driver device and said second driver device are each a MOS transistor having a large drive capability and said first holding device is a MOS transistor having a drive capability less than said first driver device or said second driver device.

46. The method of claim 43, wherein said second voltage level is substantially equal to a logic threshold level.