Reference-free clock generator and data recovery PLL

• US 6,307,413 B1
• Filed: 12/23/1999
• Issued: 10/23/2001
• Est. Priority Date: 12/23/1999
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Dalmia, Kamal, Agarwal, Anil
• Primary Examiner(s): Ton, My-Trang Nu
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US09/471,914
• Time in Patent Office: 670 Days
• Field of Search: 327/165, 327/146, 327/148, 327/150, 327/157, 327/159, 327/166, 327/47
• US Class Current: 327/166
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured generate a first output signal having a first data rate and in response to (i) an input signal having a second data rate and (ii) a clock signal having the second data rate. The second circuit may be configured to generate a second output signal having a third data rate in response to (i) a divided version of the input signal and (ii) the clock signal. The logic circuit may be configured to generate the clock signal in response to (i) the first output signal and (ii) the second output signal.

Claims

1. An apparatus comprising:

a first circuit configured to generate (a) a first output signal having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said second data rate and (b) a first data signal having said second data rate;

a second circuit configured to generate a second output signal having a third data rate in response to (i) a divided version of said input signal and (ii) said clock signal; and

a logic circuit configured to generate said clock signal in response to (i) said first output signal and (ii) said second output signal.

2. The apparatus according to claim 1, further comprising:

a divide circuit configured to generate said divided version of said input signal in response to said input signal.

3. The apparatus according to claim 1, wherein said first circuit comprises a digital linear phase detector and said second circuit comprises a digital frequency detector.

4. The apparatus according to claim 1, wherein (i) said first data signal comprises a re-timed data signal and (ii) said clock signal comprises a recovered clock signal.

5. The apparatus according to claim 1, wherein said first data rate, said second data rate and said third data rate are the same data rate or a different data rate.

6. The apparatus according to claim 1, wherein said first and said second output signals are (i) both pump-up signals, (ii) both pump-down signals or (iii) a combination of pump-up and pump-down signals.

7. The apparatus according to claim 1, wherein (i) said first output signal and/or (ii) said second output signal is configured to control said logic circuit.

8. The apparatus according to claim 1, wherein said logic circuit is configured to digitally combine said first and second output signals.

9. The apparatus according to claim 8, wherein said charge pump and filter circuit is configured to control said VCO in response to said gate.

10. The apparatus according to claim 9, wherein said apparatus comprises a half-rate phase-locked loop.

11. The apparatus according to claim 10, wherein said apparatus comprises either (i) a single loop architecture or (ii) a dual loop architecture.

12. An apparatus comprising:

means for generating (a) a first output signal having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said second data rate and (b) a first data signal having said second data rate;

means for generating a second output signal having a third data rate in response to (i) a divided version of said input signal and (ii) said clock signal; and

means for generating said clock signal in response to (i) said first output signal and (ii) said second output signal.

13. A method for clock data recovery comprising the steps of:

(A) generating a first output signal having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said second data rate and (ii) a first data signal having said second data rate;

(B) generating a second output signal having a third data rate in response to (i) a divided version of said input signal and (ii) said clock signal; and

(C) generating said clock signal in response to (i) said first output signal and (ii) said second output signal.

14. The method according to claim 13, wherein said first data signal comprises a re-timed data signal.

15. The method according to claim 13, wherein said clock signal comprises a recovered clock signal.

16. The method according to claim 13, wherein said first and second output signals are (i) both pump-up signals, (ii) both pump-down signals or (iii) a combination of pump-up and pump-down signals.

17. The method according to claim 13, wherein (i) said first and/or (ii) said second output signal controls the generation of said clock signal.

18. The method according to claim 13, wherein said step (C) further comprises adding said first and second output signals.

19. An apparatus comprising:

a first circuit configured to generate a first output signal having a first data rate and in response to (i) an input signal having a second data rate and (ii) a clock signal having said second data rate;

a second circuit configured to generate a second output signal having a third data rate in response to (i) a divided version of said input signal and (ii) said clock signal; and

a logic circuit configured to generate said clock signal in response to (i) said first output signal and (ii) said second output signal, wherein said first and said second output signals are (i) both pump-up signals, (ii) both pump-down signals or (iii) a combination of pump-up and pump-down signals.