Integrated circuit reset incorporating battery monitor and watchdog timer

• US 6,307,480 B1
• Filed: 08/01/1997
• Issued: 10/23/2001
• Est. Priority Date: 12/29/1995
• Status: Expired due to Term

• Current Assignee: Microsemi Semiconductor (U.S.) Inc. (Microchip Technology Incorporated)
• Original Assignee: Legerity Incorporated (Microsemi Semiconductor Corp.)
• Inventors: Hendrickson, Alan, Schnizlein, Paul, Sheldon, Peter
• Primary Examiner(s): Wu, Daniel J.
• Application Number:
  US08/914,017
• Time in Patent Office: 1,544 Days
• Field of Search: 340/635, 340/636, 340/660, 340/661, 327/143, 455/573, 455/127, 324/426, 324/427, 395/185.08, 395/555, 395/557, 395/559
• US Class Current: 340/636.1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: H03K 17/22 Modifications for ensuring a predetermined initial state when the supply voltage has been applied bi-stable generators H03K3/12

Abstract

A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.

Claims

1. A reset circuit for use in an integrated circuit, the reset circuit comprising:

an oscillator circuit having an oscillator disable input;

a battery monitor arranged to detect that a charge level of the battery has fallen below a predetermined charge level and having an output for indicating a charge state of a battery;

a watchdog timer having an output for indicating an operational state of software operating on the integrated circuit; and

reset logic circuitry coupled to receive the battery monitor output and the watchdog timer output and having an oscillator disable output coupled to the oscillator disable input and a reset signal output, the reset logic circuitry being configured and arranged to generate an oscillator disable signal on the oscillator disable output to disable the oscillator when both the battery monitor output and the reset signal output are active, and the reset logic circuitry further configured and arranged to generate the reset signal output if the battery monitor output or the watchdog timer output is active.

2. The reset circuit of claim 1, further comprising a level adjustment circuit connected to the reset signal output.

3. The reset circuit of claim 2, wherein the level adjustment circuit comprises circuitry external to the integrated circuit.

4. The reset circuit of claim 2, wherein the level adjustment circuit comprises only passive elements.

5. The reset circuit of claim 2, further comprising a reset defeat circuit electrically connected to the reset signal output for preventing the reset logic from generating the reset signal.

6. The reset circuit of claim 2, further comprising a reset defeat circuit electrically connected to the reset signal output for preventing the reset logic from generating the reset signal when the watchdog timer output is active but allowing the reset logic to generate the reset signal when the battery monitor output is active.

7. The reset circuit of claim 1, further comprising a reset defeat circuit electrically connected to the reset signal output for preventing the reset logic from generating the oscillator disable signal.

8. The reset circuit of claim 1, further comprising a reset extension circuit connected to receive the reset signal and having a secondary reset signal output, wherein upon receiving the reset signal, a secondary reset signal generated at the secondary reset signal output remains set for a minimum time period.

9. The reset circuit of claim 8, further comprising a microcontroller having a reset complete output connected to the reset extension circuit, wherein the secondary reset signal remains set until the reset extension circuit receives a reset complete signal on the reset complete output.

10. The reset circuit of claim 1, further comprising a first and second diode connected to the reset signal output to protect against electrostatic discharge.

11. The reset circuit of claim 1, wherein the integrated circuit is used in a wireless communication device.

12. A reset circuit for use in an integrated circuit having a microcontroller and an oscillator, the integrated circuit being powered by a battery, the reset circuit comprising:

a battery monitor for generating an output signal for indicating a low charge of the battery;

a watchdog timer for generating an output signal for indicating an operational state of the microcontroller; and

reset logic connected to receive the battery monitor output signal and the watchdog timer output signal and having a reset signal output, wherein when the battery monitor output signal is active, the reset logic disables the oscillator and resets the microcontroller and when the watchdog timer output signal is active, the reset logic resets the microcontroller but does not disable the oscillator.

13. The reset circuit of claim 12, further comprising a reset defeat circuit electrically connected to the reset signal output for preventing the reset logic from disabling the oscillator.

14. The reset circuit of claim 12, further comprising a level adjustment circuit connected to the reset signal output.

15. The reset circuit of claim 14 wherein the level adjustment circuit comprises circuitry external to the integrated circuit.

16. The reset circuit of claim 14, wherein the level adjustment circuit comprises only passive elements.

17. The reset circuit of claim 14, further comprising a reset defeat circuit electrically connected to the reset signal output for preventing the reset logic from generating the reset signal.

18. The reset circuit of claim 14, further comprising a reset defeat circuit electrically connected to the reset signal output for preventing the reset logic from generating the reset signal when the watchdog timer output is active.

19. The reset circuit of claim 12, further comprising a reset extension circuit for receiving the reset signal and having a secondary reset signal output, wherein upon receiving the reset signal, a secondary reset signal at the secondary reset signal output remains set for a minimum time period.

20. The reset circuit of claim 19, wherein the microcontroller has a reset complete output connected to the reset extension circuit, wherein the secondary reset signal remains set until the reset extension circuit receives the reset complete signal on the reset complete output.

21. The reset circuit of claim 12, further comprising a first and second diode connected to the reset signal output to protect against electrostatic discharge.

22. The reset circuit of claim 12, wherein the integrated circuit is used in a wireless communication device.

23. A reset circuit in an integrated circuit having a microcontroller and an oscillator, the integrated circuit powered by a battery, the reset circuit comprising:

means for monitoring a charge state of the battery;

means for monitoring an operational state of the microcontroller;

means for activating a reset signal when the charge monitoring means indicates a low charge of the battery or the microcontroller monitoring means indicates a predetermined operational state of the microcontroller; and

means for disabling the oscillator only when both the battery monitoring means indicates a low charge of the battery and the reset signal is active.

24. The reset circuit of claim 23, further comprising means for adjusting a level of the reset signal.

25. The reset circuit of claim 23, further comprising means for preventing generation of the reset signal.

26. The reset circuit of claim 23, further comprising means for asserting the reset signal until it is released by the microcontroller.

27. A method for implementing a reset operation in an integrated circuit having a microcontroller and an oscillator, the integrated circuit powered by a battery, the method comprising:

monitoring a charge state of the battery;

monitoring an operational state of the microcontroller;

generating a reset signal when the charge monitoring indicates a low charge of the battery or the microcontroller monitoring indicates an error in the operational state of the microcontroller; and

disabling the oscillator only when both the battery monitoring means indicates a low charge of the battery and the reset signal is generated.

28. The method of claim 27, further comprising adjusting a level of the reset signal.

29. The method of claim 27, further comprising preventing generation of the reset signal.

30. The reset circuit of claim 27, further comprising asserting the reset signal until it is released by the microcontroller.