Programmable gain ADC

• US 6,307,497 B1
• Filed: 08/11/2000
• Issued: 10/23/2001
• Est. Priority Date: 06/19/2000
• Status: Expired due to Term

• Current Assignee: Silicon Labs CP, Inc. (Silicon Laboratories Incorporated)
• Original Assignee: Cygnal Integrated Products, Inc. (Silicon Laboratories Incorporated)
• Inventors: Leung, Ka Y., Piasecki, Douglas S.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US09/638,095
• Time in Patent Office: 438 Days
• Field of Search: 341/155, 341/159, 341/144, 341/139
• US Class Current: 341/155
• CPC Class Codes: H03M 1/129 Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling H03M1/18 takes precedence; Out-of-range indication
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter

Abstract

A programmable gain circuit for analog-to-digital converter. A switched capacitor network capacitively couples an analog reference from a DAC to a comparator so that the sampled amplitude of the input analog signal can be compared with said analog reference. The ratio of the capacitance of the sampling capacitor to that of the switched capacitor network establishes an effective gain to the analog signal being converted.

Claims

1. A programmable gain circuit for an analog-to-digital converter, comprising:

a sampling capacitor for storing a sample of a voltage representative of an analog signal to be converted to a corresponding digital signal;

a comparator circuit for comparing said sampled voltage with a reference analog signal;

a digital-to-analog converter (DAC) for generating said reference analog signal; and

a switched capacitor circuit, including a plurality of switched capacitors coupled between an output of said DAC and an input circuit of said comparator, wherein a desired gain can be achieved as a function of a switched arrangement of said switched capacitors.

2. The programmable gain circuit of claim 1, wherein said switched capacitor circuit is coupled to said sampling capacitor so that electrical charge is shared therebetween.

3. The programmable gain circuit of claim 2, wherein an output of said switched capacitor circuit is connected to one plate of said sampling capacitor.

4. The programmable gain circuit of claim 3, wherein an input of said comparator is coupled to a junction between said sampling capacitor and said switched capacitor circuit.

5. The programmable gain circuit of claim 1, further including a switch arrangement for switching said switched capacitors in parallel to thereby change the gain of the analog-to-digital converter.

6. The programmable gain circuit of claim 5, wherein said switched capacitors are switched to increase a total capacitance of the switched capacitor circuit to lower the gain of the analog-to-digital converter.

7. The programmable gain circuit of claim 6, wherein said switched capacitors have different capacitances to provide corresponding different gains.

8. The programmable gain circuit of claim 1, further including a switch for connecting one terminal of said sampling capacitor to a circuit common voltage to thereby couple an inverted polarity analog signal amplitude for comparison by said comparator.

9. The programmable gain circuit of claim 1, further including a second sampling capacitor so that differential analog signal amplitudes can be sampled, and further including a switch for connecting said sampling capacitors in series.

10. A method of providing gain in an analog-to-digital converter circuit, comprising the steps of:

coupling an analog signal amplitude via an input capacitor to a node;

coupling an analog reference via a switched capacitor network to said node;

comparing a voltage representative of the voltage of said node with a second voltage to produce a digital signal; and

switching a number of capacitors in said switched capacitor network to vary a capacitance thereof for adjusting the magnitude of the analog reference relative to the magnitude of the analog signal amplitude at said node.

11. The method of claim 10, wherein said switched capacitor network includes a plurality of capacitors and a plurality of switches to connect two or more said switched capacitors in parallel.

12. The method of claim 11, further including increasing the capacitance of said switched capacitor network to lower the gain of the analog-to-digital converter circuit.

13. The method of claim 10, further including AN SAR responsive to said digital signal for producing a digital word, and, for a given analog signal amplitude, switching in additional capacitances in said switched capacitor network to thereby require a larger magnitude analog reference coupled via said switched capacitor network to said node, thereby requiring a derivation of a larger value digital word.

14. The method of claim 10, wherein said input capacitor defines a first capacitor, and further including coupling differential analog amplitudes to respective first and second input capacitors, and connecting said first and second input capacitors in series.

15. The method of claim 14, wherein said first and second input capacitors are of substantially equal capacitance value.

16. The method of claim 10, further including applying said digital signal to a successive approximation register circuit to derive a digital word corresponding to said analog signal amplitude.

17. The method of claim 10, further including connecting one terminal of said input capacitor to a common voltage to thereby couple an inverted polarity analog signal amplitude to said node.

18. A programmable gain circuit for an analog-to-digital converter, comprising:

a comparator circuit for generating a digital signal as a function of voltages applied to inputs thereof;

at least one input capacitor for transferring an analog signal amplitude to a node for comparing by said comparator;

a digital-to-analog converter for generating a reference voltage as a function of a digital word input thereto; and

a switched capacitor network including a plurality of capacitors, and a plurality of switches for activating and deactivating ones of said switched capacitors, a first terminal of said switched capacitor network driven by said reference voltage, and a second terminal of said switched capacitor network driving said node, whereby for effective larger capacitances generated by said switched capacitor network a smaller reference voltage is required to drive said switched capacitor network to produce a voltage at said node substantially equal in magnitude to said analog signal amplitude, thereby effectively lowering the gain of said analog-to-digital converter.

19. The programmable gain circuit of claim 18, wherein said switched capacitor network drives said node with a signal polarity opposite that applied to said node by said input capacitor.

20. The programmable gain circuit of claim 19, further including a switch coupled to said input capacitor and operable for causing a sampled voltage stored by said input capacitor to be inverted in polarity when transferred to said node.

21. The programmable gain circuit of claim 18, further including an arrangement of switched capacitors and switches for providing a gain of less than unity.