System for dual buffering of asynchronous input to dual port memory for a raster scanned display

• US 6,307,565 B1
• Filed: 12/23/1998
• Issued: 10/23/2001
• Est. Priority Date: 12/23/1998
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell International Inc.
• Inventors: Hancock, William Ray, Quirk, Robert John
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/220,234
• Time in Patent Office: 1,035 Days
• Field of Search: 345/539, 345/545, 345/554, 345/564, 365/230.05, 365/230.01, 365/184.01, 365/189.04, 365/230.03, 365/230.04
• US Class Current: 345/554
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A system which utilizes two buffers of dual-port memory to seamlessly display video frames on a raster scanned video display device. Dual port memory is organized into two alternate memory banks, each having sufficient capacity to buffer a full frame of video data. As long as the display memory write and read addresses are sufficiently separated by a predetermined number of lines, video data is written and read using alternate banks of memory for each frame. When the write and read addresses are closer than a predetermined number of lines, the video data already stored in a given bank of memory is re-read. After the write and read addresses are again sufficiently separated, video data is again written and read using alternate banks of memory.

Claims

1. A method for controlling the reading from and writing to dual-port memory used for storing digital video data to be displayed on a raster scanned video display device, the video data being written to a write address in said memory and being read from a read address in said memory, wherein the video data is received asynchronously with respect to the video frame display rate, and wherein said dual-port memory includes two memory banks which are alternate banks to one another, the method comprising the steps of:

receiving a read sync signal;

determining a separation between a present said read address and a present write address;

reading said video data for the next said frame from said alternate memory bank if said separation is greater than a predetermined number of lines;

re-reading said video data stored in a present one of said memory banks if said separation is not greater than a predetermined number of lines; and

writing each successive said frame of said video data to said alternate bank after each write sync signal is received,

wherein said present one of said memory banks contains a most recent frame of said video data.

2. The method of claim 1, wherein each of said memory banks has a storage capacity of at least one said frame of said video data.

3. The method of claim 1, wherein said video display device is selected from the group consisting of an LCD display, a plasma display, a field emission display, and a CRT display.

4. A system for controlling the reading from and writing to dual-port memory for storing digital video data to be displayed on a raster scanned video display device, the video data being written to a write address in said memory and being read from a read address in said memory, wherein the video data is received asynchronously with respect to the video frame display rate, the system comprising:

a first flip-flop having an input connected to a write sync signal source;

a second flip-flop;

two banks of dual-port memory, wherein a first output and a second output from said first flip-flop are connected to a write port enable input on a first one and a second one of said banks, respectively, and wherein a first output and a second output of said second flip-flop are connected to a read port enable input on a first one and a second one of said banks, respectively;

address compare logic having an input connected to a read sync signal source and to read address and write address lines on each of said banks, and having an output connected to a clock input of said second flip-flop, said output being an alternate buffer output signal generated in response to a simultaneous presence of said read sync signal and a predetermined separation between said read address and said write address;

wherein said display device is connected to a data output port of each of said banks;

wherein each occurrence of said write sync signal causes said first flip-flop to toggle an output signal between said write port enable input on said first one of said banks and said write port enable input on said second one of said banks, and

wherein said alternate buffer signal causes said first flip-flop to toggle an output signal between said read port enable input on said first one of said banks and said read port enable input on said second one of said banks.

5. The system of claim 4, wherein each of said banks of dual port memory has a storage capacity of at least one said frame of said video data.

6. The system of claim 4, wherein said video display device is selected from the group consisting of an LCD display, a plasma display, a field emission display, and a CRT display.

7. A system for controlling the reading from and writing to dual-port memory for storing digital video data to be displayed on an LCD display, the video data being written to a write address in said memory and being read from a read address in said memory, wherein the video data is received asynchronously with respect to the LCD frame display rate, the system comprising:

two dual-port memory banks, each having a write port enable input and a read port enable input;

read sync indication means, responsive to a simultaneous presence of said read sync signal and a predetermined separation between said read address and said write address, for generating an alternate buffer signal indicating that said write address and said read address are separated by a predetermined distance;

first flip-flop means, responsive to a write sync signal, for toggling an output signal between said write port enable input on said first one of said banks and said write port enable input on said second one of said banks;

second flip-flop means, responsive to said alternate buffer signal, for toggling an output signal between said read port enable input on said first one of said banks and said read port enable input on said second one of said banks.

8. The system of claim 7, wherein each of said dual-port memory banks has a storage capacity of one said frame of said video data.

9. The system of claim 7, wherein said video display device is selected from the group consisting of an LCD display, a plasma display, a field emission display, and a CRT display.