Multi-bit-per-cell flash EEPROM memory with refresh

• US 6,307,776 B1
• Filed: 10/06/2000
• Issued: 10/23/2001
• Est. Priority Date: 09/08/1997
• Status: Expired due to Fees

• Current Assignee: SanDisk Corporation (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: So, Hock C., Wong, Sau C.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/680,797
• Time in Patent Office: 382 Days
• Field of Search: 345/185.03, 345/185.09, 345/185.22, 345/185.24, 345/185.25, 345/189.02, 345/184, 345/230.02, 371/21.4, 371/21.1
• US Class Current: 365/185.03
• CPC Class Codes: B64C 27/006 Safety devices
• CPC Class Codes: G01N 29/14 using acoustic emission techniques echo of particles G01N29/046; measuring mechanical vibrations or acoustic waves in solids in general G01H1/00
• CPC Class Codes: G01N 29/227 related to high pressure, tension or stress conditions
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.

Claims

1. A method for operating a non-volatile memory comprising a plurality of sectors, comprising:

programming threshold voltages of memory cells in the non-volatile memory to have a threshold voltage in an allowed state associated with a data value stored in the memory cell, wherein threshold voltages of the memory cells have a plurality of allowed states that are separated from each other by forbidden zones;

identifying a first sector of the non-volatile memory that contains a memory cell with a threshold voltage in one of the forbidden zones; and

refreshing the data values stored in memory cells in the identified first sector, the refreshing comprising;

reading data values from the first sector; and

writing the data values in a second sector.

2. The method of claim 1, wherein the refreshing further comprises:

storing the data values read from the first sector in a buffer prior to said writing the data values in a second sector.

3. The method of claim 1, wherein said refreshing is performed in response to a signal from a timer.

4. The method of claim 3, wherein said refreshing is performed periodically with a period greater than one day.

5. The method of claim 3, further comprising determining a time during which use of the memory is unlikely, wherein the timer schedules refreshing for that time.

6. The method of claim 1, wherein said refreshing is performed as part of a power up procedure for the memory.

7. The method of claim 1, wherein reading the data values comprises measuring the threshold voltage of the memory cell with the threshold voltage in one of the forbidden zones, wherein a data value read from that memory cell corresponds to an allowed state near the forbidden zone containing the threshold voltage of the memory cell.

8. A method for operating a non-volatile memory, comprising:

comparing the threshold voltage of a memory cell in analog form with a plurality of reference voltages simultaneously;

identifying whether the threshold voltage is in one of a first plurality of ranges of threshold voltages or in a second plurality of threshold voltages, wherein said pluralities of ranges are determined from said reference voltages; and

in response to the threshold voltage being in the first plurality of threshold voltages, changing the threshold voltage so that the threshold voltage is in one of the second plurality of ranges of threshold voltages.

9. The method of claim 8, wherein:

the second plurality of ranges of threshold voltages form a sequence of ranges ordered according to increasing maximum voltages of the ranges;

each range corresponds to a different multibit digital value; and

the multibit digital value for each range differs by only one bit, from the multibit value for the range immediately preceding in the series.

10. The method of claim 8, wherein said method is performed as part of a standard read operation for the memory.

11. The method of claim 8, wherein changing the threshold voltage increases the threshold voltage so that the threshold voltage is in a nearest one of the second ranges.

12. The method of claim 12, wherein changing the threshold voltage decreases the threshold voltage so that the threshold voltage is in a nearest one of the second ranges.

13. A non-volatile semiconductor memory comprising:

an array of memory cells;

a reference generator generating a plurality of reference voltages, whereby a plurality of first voltage ranges and one or more second voltage ranges are determined;

a comparator circuit coupled to said array and to said reference generator, whereby the analog threshold value of a memory cell is compared to a plurality of said reference voltages simultaneously during a read process;

a write circuit coupled to said array; and

a control circuit coupled to the write circuit and the comparator circuit, whereby in response to the comparator determining during a read process that the threshold voltage of a memory cell is in one of the second voltage ranges, said write circuit initiates a process to write said memory cell to one of the first voltage ranges.

14. The non-volatile semiconductor memory of claim 13, wherein the first voltage ranges indicate bounds of ranges of threshold voltages allowed for the memory cells storing data and the second voltage ranges are threshold voltages forbidden for the memory cells storing data.

15. The non-volatile semiconductor memory of claim 14, wherein the ranges of threshold voltages allowed for memory cells storing data are separated from each other by at least one range of threshold voltages forbidden for memory cells storing data.

16. The non-volatile semiconductor memory of claim 13, wherein the non-volatile semiconductor memory is part of a monolithic integrated circuit.