Dynamic random access memory
First Claim
1. A semiconductor memory device, comprising:
- dynamic memory cells arranged in a row and column array, each of said dynamic memory cells comprising a transfer MOS transistor of a first conductivity type and a capacitive element coupled to said transfer MOS transistor for storing data;
word lines each connecting the dynamic memory cells in one row of said array;
bit lines each connecting the dynamic memory cells in one column of said array;
pads to which receiving external address signals are applied;
address amplifying circuits responsive to the external address signals applied to the pads for generating first internal address signals selecting a first number of said word lines in a normal operation mode;
a word line driving voltage source;
word line selecting circuits responsive to the first internal address signals for outputting word line selecting signals, said word line selecting circuits each comprising a logic gate for decoding the first internal address signals and a precharge transistor having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to an output of said logic gate, and a control terminal receiving a precharge signal for precharging the output of said logic gate;
a control circuit responsive to a voltage stress test control signal for selecting a second number of said word lines in a voltage stress test operation mode, the second number being greater than the first number; and
word line driving circuits coupled between corresponding ones of said word line selecting circuits and said word line, said word line driving circuits having first and second transistors, the first transistor of a second conductivity type having a first current terminal to which a voltage from said word line driving voltage source is applied, a second current terminal coupled to the corresponding one of said word lines, and a control terminal coupled to the corresponding one of said word line selecting circuits, and the second transistor of the first conductivity type having a first current terminal coupled to the corresponding one of said word lines, a second current terminal coupled to the ground potential, and a control terminal coupled to the corresponding one of said word line selecting circuits.
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Accused Products
Abstract
A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.
22 Citations
4 Claims
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1. A semiconductor memory device, comprising:
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dynamic memory cells arranged in a row and column array, each of said dynamic memory cells comprising a transfer MOS transistor of a first conductivity type and a capacitive element coupled to said transfer MOS transistor for storing data;
word lines each connecting the dynamic memory cells in one row of said array;
bit lines each connecting the dynamic memory cells in one column of said array;
pads to which receiving external address signals are applied;
address amplifying circuits responsive to the external address signals applied to the pads for generating first internal address signals selecting a first number of said word lines in a normal operation mode;
a word line driving voltage source;
word line selecting circuits responsive to the first internal address signals for outputting word line selecting signals, said word line selecting circuits each comprising a logic gate for decoding the first internal address signals and a precharge transistor having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to an output of said logic gate, and a control terminal receiving a precharge signal for precharging the output of said logic gate;
a control circuit responsive to a voltage stress test control signal for selecting a second number of said word lines in a voltage stress test operation mode, the second number being greater than the first number; and
word line driving circuits coupled between corresponding ones of said word line selecting circuits and said word line, said word line driving circuits having first and second transistors, the first transistor of a second conductivity type having a first current terminal to which a voltage from said word line driving voltage source is applied, a second current terminal coupled to the corresponding one of said word lines, and a control terminal coupled to the corresponding one of said word line selecting circuits, and the second transistor of the first conductivity type having a first current terminal coupled to the corresponding one of said word lines, a second current terminal coupled to the ground potential, and a control terminal coupled to the corresponding one of said word line selecting circuits. - View Dependent Claims (2, 3, 4)
a pad for receiving an externally supplied word line driving voltage during the voltage stress test operation mode;
a switching circuit having a first input terminal coupled to said word line driving voltage source, a second input terminal coupled to said pad, and an output terminal coupled to said first current terminal of said second MOS transistor, said switching circuit supplying a voltage output by said word line driving voltage source during the normal operation mode and supplying a voltage received at said pad during the voltage stress test operation mode.
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Specification