Nonvolatile semiconductor memory

• US 6,307,807 B1
• Filed: 09/09/1999
• Issued: 10/23/2001
• Est. Priority Date: 09/10/1998
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Miyamoto, Junichi, Sakui, Koji
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/393,201
• Time in Patent Office: 775 Days
• Field of Search: 365/238.5, 365/185.01, 365/185.05, 365/185.33, 365/185.29, 365/185.11
• US Class Current: 365/238.5
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Claims

1. A nonvolatile semiconductor memory comprising:

a memory cell array having a memory cell unit formed from a memory cell and two select transistors sandwiching the memory cell;

a bit line connected to one of the select transistors; and

a sense amplifier connected to said bit line and having a latch function,

wherein the memory cell and the select transistors are connected in series, and the memory cell has a stacked gate structure having a floating gate and a control gate.

2. A memory according to claim 1, wherein

each of the two select transistors has the same structure as the memory cell.

3. A memory according to claim 1, further comprising

means for, when data are to be changed for selected memory cells in memory cells of one page connected to a selected control gate line in said memory cell array, reading data of the memory cells of one page to said sense amplifiers, superscribing, in said sense amplifiers, data on data corresponding to the selected memory cells of the page, erasing the data of the memory cells of one page, and programming the data of said sense amplifiers in the memory cells of one page.

4. A memory according to claim 3, wherein

the data corresponding to the selected memory cells constitute one of byte data and page data.

5. A memory according to claim 3, wherein an operation of changing the data is constituted by an erase operation and a program operation, the program operation being performed by a hot electron phenomenon, and the erase operation being performed by the F-N tunneling phenomenon.

6. A nonvolatile semiconductor memory comprising:

a memory cell array having a first memory cell unit formed from a memory cell and two select transistors sandwiching the memory cell and a second memory cell unit formed from a plurality of memory cells;

a bit line commonly connected to the first and second memory cell units; and

a sense amplifier connected to said bit line and having a latch function,

wherein the memory cell and the select transistors in said first memory cell unit are connected in series, and each of the memory cells in the first and second memory cell units has a stacked gate structure having a floating gate and a control gate.

7. A memory according to claim 6, wherein

the second memory cell unit comprises one of a NAND unit in which the plurality of memory cells are connected in series, an AND unit in which the plurality of memory cells are connected in parallel, and a DINOR unit in which the plurality of memory cells are connected in parallel.

8. A memory according to claim 6, wherein

each of the two select transistors has the same structure as the memory cell.

9. A memory according to claim 6, further comprising

means for, when data are to be changed for selected memory cells in memory cells of one page connected to a selected control gate line in said memory cell array, reading data of the memory cells of one page to said sense amplifiers, superscribing, in said sense amplifiers, data on data corresponding to the selected memory cells of the page, erasing the data of the memory cells of one page, and programming the data of said sense amplifiers in the memory cells of one page.

10. A memory according to claim 9, wherein

the data corresponding to the selected memory cells constitute one of byte data and page data.

11. A memory according to claim 9, wherein an operation of changing the data is constituted by an erase operation and a program operation, the program operation being performed by a hot electron phenomenon, and the erase operation being performed by the F-N tunneling phenomenon.

12. A nonvolatile semiconductor memory comprising:

a memory cell array formed from memory cell units each including a memory cell;

a bit line connected to the memory cell units;

a sense amplifier connected to said bit line and having a latch function; and

means for, when data are to be changed for selected memory cells in memory cells of one page connected to a selected control gate line in said memory cell array, reading data of the memory cells of one page to said sense amplifiers, superscribing, in said sense amplifiers, data on data corresponding to the selected memory cells of the page, erasing the data of the memory cells of one page, and programming the data of said sense amplifiers in the memory cells of one page.

13. A memory according to claim 12, wherein

the memory cell unit comprises one of a memory cell unit having a memory cell and two select transistors sandwiching the memory cell, a NAND unit in which a plurality of memory cells are connected in series, an AND unit in which a plurality of memory cells are connected in parallel, and a DINOR unit in which a plurality of memory cells are connected in parallel.

14. A memory according to claim 12, wherein

the data corresponding to the selected memory cells constitute one of byte data and page data.

15. A memory according to claim 12, wherein an operation of changing the data is constituted by an erase operation and a program operation, the program operation being performed by a hot electron phenomenon, and the erase operation being performed by the F-N tunneling phenomenon.

16. A nonvolatile semiconductor memory comprising:

a memory cell array having first and second memory cell units each formed from a memory cell and two select transistors sandwiching the memory cell;

a first bit line connected to one of the two select transistors in the first memory cell unit;

a second bit line connected to one of the two select transistors in the second memory cell unit; and

a sense amplifier connected to each of said first and second bit lines and having a latch function,

wherein the memory cell and the select transistors in said first and second memory units are connected in series.

17. A nonvolatile semiconductor memory device comprising:

a memory cell array having a memory cell unit formed from a plurality of memory cells and two select transistors sandwiching the memory cells;

a bit line connected to one of the two select transistors;

a sense amplifier connected to said bit line and having a latch function; and

means for, in a program operation, applying a program potential higher than a power supply potential to a selected control gate line in said memory cell array and, applying the power supply potential or a read potential to an unselected control gate line in said memory cell array in a read operation.

18. A memory according to claim 17, wherein

the memory cell unit includes two memory cells.

19. A memory according to claim 17, wherein

each of the plurality of memory cells has a stacked gate structure having a floating gate and a control gate.

20. A memory according to claim 19, wherein

each of the two select transistors has the same structure as the plurality of memory cells.

21. A memory according to claim 17, further comprising

means for, when data are to be changed for selected memory cells in memory cells of one page connected to a selected control gate line in said memory cell array, reading data of the memory cells of one page to said sense amplifiers, superscribing, in said sense amplifiers, data on data corresponding to the selected memory cells of the page, erasing the data of the memory cells of one page, and programming the data of said sense amplifiers in the memory cells of one page.

22. A memory according to claim 21, wherein

the data corresponding to the selected memory cells constitute one of byte data and page data.

23. A memory according to claim 21, wherein an operation of changing the data is constituted by an erase operation and a program operation, the program operation being performed by a hot electron phenomenon, and the erase operation being performed by the F-N tunneling phenomenon.

24. A memory according to claim 17, wherein

in the program operation, said means applies the power supply potential or the read potential to the selected control gate line and the unselected control gate line and then increases only the potential of the selected control gate line to the program potential.

25. A nonvolatile semiconductor memory comprising:

a memory cell array having a first memory cell unit formed from a plurality of memory cells and two select transistors sandwiching the memory cells and a second memory cell unit having a plurality of memory cells;

a bit line commonly connected to the first and second memory cell units;

a sense amplifier connected to said bit line and having a latch function; and

means for, in a program operation, when a block including the first memory cell unit is selected, applying a program potential higher than a power supply potential to a selected control gate line in said memory cell array and, applying the power supply potential or a read potential to an unselected control gate line in said memory cell array in a read operation.

26. A memory according to claim 25, wherein

the second memory cell unit comprises one of a NAND unit in which the plurality of memory cells are connected in series, an AND unit in which the plurality of memory cells are connected in parallel, and a DINOR unit in which the plurality of memory cells are connected in parallel.

27. A memory according to claim 25, further comprising

means for, when data are to be changed for selected memory cells in memory cells of one page connected to a selected control gate line in said memory cell array, reading data of the memory cells of one page to said sense amplifiers, superscribing, in said sense amplifiers, data on data corresponding to the selected memory cells of the page, erasing the data of the memory cells of one page, and programming the data of said sense amplifiers in the memory cells of one page.

28. A memory according to claim 27, wherein

the data corresponding to the selected memory cells constitute one of byte data and page data.

29. A memory according to claim 27, wherein an operation of changing the data is constituted by an erase operation and a program operation, the program operation being performed by a hot electron phenomenon, and the erase operation being performed by the F-N tunneling phenomenon.

30. A memory according to claim 25, wherein

in the program operation, said means applies the power supply potential or the read potential to the selected control gate line and the unselected control gate line and then increases only the potential of the selected control gate line to the program potential.