Programmable modem apparatus for transmitting and receiving digital data, design method and use method for the modem

• US 6,307,877 B1
• Filed: 08/21/1998
• Issued: 10/23/2001
• Est. Priority Date: 10/04/1995
• Status: Expired due to Term

• Current Assignee: Keysight Technologies, Inc., SAIT Systems
• Original Assignee: IMEC International
• Inventors: De Man, Hugo, Vanhoof, Jan, Van Himbeeck, Carl, Philips, Lieven, Wouters, Maryse, Gyselinckx, Bert, Bolsens, Ivo, De Wulf, Rik, Derudder, Veerle
• Primary Examiner(s): Ghebretinsae, Temesghen
• Application Number:
  US09/138,162
• Time in Patent Office: 1,159 Days
• Field of Search: 375/200, 375/208, 375/222, 375/219, 375/295
• US Class Current: 375/130
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 8/10 Requirements analysis; Specification techniques
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 2201/7071 with dynamic control of receiver resources

Abstract

The programmable modem for digital data of the present invention provides a highly programmable, digital modem implemented in an integrated circuit which can be customized to specific applications. The programmable modem uses spread spectrum techniques and is specifically programmable to alter the parameters of the modem to improve performance. The present invention also provides a systematic method and development kit to provide rapid customization of a modem for a particular application or for rapid specification of a high-performance application specific integrated circuit mode.

Claims

1. A system for transmitting and receiving signals, comprising:

a digital integrated circuit having a transmitter which generates first baseband signals, said transmitter having a first plurality of circuits comprising a converter coupled to receive parallel input data signals and which converts said parallel input data to serial data, a spreader, an over-sampling filter, a gain control, and an up-converter which converts said first baseband signals to first intermediate frequency signals;

a receiver having a plurality of circuits to generate a plurality of output data signals, said plurality of circuits comprising a down-converter to convert second signals at an intermediate frequency to second baseband signals, a decimating filter, a gain control, and a correlator which generates said plurality of output data signals;

a clock generator coupled to said transmitter and said receiver, said clock generator having at least one numerically controlled oscillator;

at least one memory mapped memory which provides storage locations for programming of said digital integrated circuit;

a phase error measuring module which measures a phase error between an external signal and one of said plurality of output data signals;

a processor coupled to said digital integrated circuit, said processor writing parameters to said storage locations and reading said plurality of output data signals and the phase error; and

a memory mapped interface coupled between said processor and said digital integrated circuit.

2. The system of claim 1, wherein said at least one memory comprises:

a code phase storage memory, a spreading code storage memory, and a spreading code length storage memory for said transmitter;

a gain control programming memory for said transmitter;

a up-converter frequency memory;

a transmitter modulation procedure selection memory; and

an over-sampling filter interpolation factor memory for said transmitter.

3. The system of claim 2, further wherein said spreading codes and said spreading code lengths are PN codes and PN code lengths.

4. The system of claim 2, further comprising data and address busses connecting said memory mapped interface with said at least one memory, and address decoders responsive to the address of the at least one memory via said memory mapped interface.

5. The system of claim 2, further comprising:

a memory for storage of a code phase, spreading codes and spreading code lengths of said correlator, with a granularity of half a code bit period;

a gain control memory which stores the gain control factor for said receiver;

a down-converter frequency storage memory;

a demodulation procedure selection memory for said receiver;

a decimation factor storage memory for said decimating filter; and

a clock frequency memory for said clock generators.

6. The system of claim 5, further comprising data and address busses connecting said memory mapped interface with said at least one memory, and address decoders responsive to the address of the at least one memory via said memory mapped interface.

7. The system of claim 4, further comprising means for programming the codes of said correlator and of said spreader with a maximal code length of 1024.

8. The system of claim 1, further comprising:

a filter in said first plurality of circuits which shapes the spreaded first baseband signals for bandwidth reduction;

a filter in said second plurality of circuits which performs out-of-band noise filtering on the down-converted second baseband signals.

9. The system of claim 8, wherein said up-converter and said down-converter comply with the CORDIC algorithm.

10. The system as recited in claim 1, further comprising an external pilot demodulator, an external traffic demodulator, and an external noise estimator.

11. The system recited in claim 10, wherein said correlator generates said plurality of output data signals for said external pilot demodulator, said external traffic demodulator and said external noise estimator, said correlator comprising:

a random access memory for storage of a plurality of PN codes comprising a plurality of pilot codes and a plurality of traffic codes;

a pilot correlator coupled to receive an output signal of said decimating filter and which correlates said decimating filter output signal with said pilot codes to generate said output data signals;

a traffic correlator coupled to receive said output signal of said decimating filter and which correlates said decimating filter output signal with said with said traffic codes to generate second output data signals;

a code phase control circuit comprising having an address generation circuit for said random access memory and having a clock inhibit circuit with a cycle of half a code bit period;

a symbol timing circuit having an interrupt signal generator which generates an interrupt signal for said processor when data is ready.

12. The system of claim 11, wherein said digital integrated circuit is an application specific integrated circuit.

13. The system of claim 12, wherein said application specific integrated circuit is a domain specific integrated circuit.

14. The system of claim 13, wherein said system is integrated in a multi-chip module package.

15. A method of digitally combining low rate input data signals with accurately defined up-converter and down-converter intermediate frequencies comprising the step of using the system of claim 7 to program an interpolation factor with a value high enough to obtain accurately defined up-converter and down-converter frequencies.

16. A method for processing spread spectrum signals, comprising the steps of:

dividing an input data signal among a plurality of parallel segments of transmission data;

spreading each of the plurality of parallel segments to form parallel spread signals using orthogonal or semi-orthogonal PN codes;

summing the parallel spread signals to generate a sum signal;

digital filtering the sum signal to generate a first baseband signal;

converting said first baseband signal to an intermediate frequency signal and transmitting said intermediate frequency signal; and

receiving said intermediate frequency signal and converting, to a second baseband signal, said receiving and converting completed in a receiver with parallel correlators synchronized to despread said sum signal.

17. The method of claim 16, comprising the step of realizing the method in an integrated circuit.