Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications

• US 6,308,055 B1
• Filed: 05/29/1998
• Issued: 10/23/2001
• Est. Priority Date: 05/29/1998
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Wang, Caiyi, Welland, David R.
• Primary Examiner(s): Hunter, Daniel
• Assistant Examiner(s): Corsaro, Nick
• Application Number:
  US09/087,486
• Time in Patent Office: 1,243 Days
• Field of Search: 455/260, 455/76, 455/119, 331/177.R, 331/177.V, 331/37
• US Class Current: 455/260
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

Claims

1. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator having an output frequency dependent upon a capacitance amount within an LC tank resonant structure;

a plurality of parallel-connected continuously variable capacitor circuits that together provide at least part of the capacitance amount, each capacitor circuit having a control signal configured to determine at least in part an amount of capacitance that is contributed by that capacitor circuit to the capacitance amount;

a first clock node coupled to an output of the controllable oscillator;

a second clock node coupled to a reference clock; and

a plurality of different control signals coupled to inputs of the controllable oscillator to provide said control signals to the plurality of variable capacitor circuits, the control signals being generated from, at least in part, a phase difference between a first clock signal on the first clock node that is related to the output frequency and a second clock signal on the second clock node that is related to the reference frequency, wherein the control signals are continuously variable analog signals.

2. The frequency synthesizer of claim 1, further comprising a plurality of phase shifted signals, the phase shifted signals being generated from, at least in part, the first clock signal that is related to the output frequency, and wherein the plurality of control ignals are generated from a phase difference between at least some of the plurality of phase shifi d signals and the second clock signal that is related to the reference frequency.

3. The frequency synthesizer of claim 2, wherein the plurality of control signals is comprised of at least five control signals each connected to at least one different variable capacitor circuit.

7. The frequency synthesizer of claim 1, further comprising a master control signal generated utilizing the first and second clock signals, wherein the master control signal is used to generate the plurality of control signals.

8. The frequency synthesizer of claim 7, wherein the master control signal is indicative of the phase difference between the first and second clock signals.

9. The frequency synthesizer of claim 8, wherein the master control signal has a voltage level which varies with the phase difference between the first and second clock signals.

10. The frequency synthesizer of claim 1, wherein the plurality of control signals is comprised of at least twenty control signals each connected to at least one different variable capacitor circuit.

11. The frequency synthesizer of claim 1, wherein the plurality of control signals is comprised of at least five control signals each connected to at least one different variable capacitor circuit.

14. The frequency synthesizer of claim 1, wherein each of the variable capacitor circuits comprises a first capacitor and a second capacitor coupled in series between the two common nodes, a third node being located between the first and second capacitors, and a variable resistance element configured to receive at least one of the control signals and being coupled between the third node and one of the common nodes.

33. The frequency synthesizer of claim 1, further comprising:

a sample and hold circuit coupled to at least one input of the controllable oscillator, the sample and hold circuit having at least one sample and hold output that provides at least one of the plurality of control signals.

35. The frequency synthesizer of claim 1, further comprising:

a sample and hold circuit coupled to the plurality of controllable oscillator inputs, the sample and hold circuit outputs providing the analog control signals.

4. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator having an output frequency dependent upon a capacitance amount within an LC tank resonant structure;

a plurality of parallel-connected variable capacitor circuits within the controllable oscillator that together provide at least part of the capacitance amount, each capacitor circuit having a control signal configured to determine at least in part an amount of capacitance that is contributed by that capacitor circuit to the capacitance amount;

a first clock node coupled to an output of the controllable oscillator;

a second clock node coupled to a reference clock;

a plurality of different control signals coupled to inputs of the controllable oscillator to provide said control signals to the plurality of variable capacitor circuits, the control signals being generated from, at least in part, from a phase difference between a first clock signal on the first clock node that is related to the output frequency and a second clock signal on the second clock node that is related to the reference frequency;

a plurality of phase shifted signals, the phase shifted signals being generated from, at least in part, the first clock signal, and wherein the plurality of control signals are generated from a phase difference between at least some of the plurality of phase shifted signals and the second clock signal; and

a shift register operatively coupled to the first clock node for generating the plurality of phase shifted signals.

5. The frequency synthesizer of claim 4, further comprising a phase detector connected between the shift register and the controllable oscillator for converting the plurality of phase shifted signals to the plurality of control signals.

6. The frequency synthesizer of claim 5, further comprising a reference clock signal operatively connected to the phase detector, wherein the phase detector detects a phase difference between the phase shifted signals and the reference clock signal.

12. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator having an output frequency dependent upon a capacitance amount within an LC tank resonant structure, wherein the controllable oscillator further comprises a plurality of parallel-connected continuously variable capacitor circuits that together provide at least part of the capacitance amount, each capacitor circuit having a control signal configured to determine at least in part an amount of capacitance that is contributed by that capacitor circuit to the capacitance amount;

a first clock node coupled to an output of the controllable oscillator;

a second clock node coupled to a reference clock;

a plurality of control signals coupled to inputs of the controllable oscillator to provide said control signals to the plurality of variable capacitor circuits, the control signals being generated from, at least in part, from a phase difference between a first clock signal on the first clock node that is related to the output frequency and a second clock signal on the second clock node that is related to the reference frequency.

13. The frequency synthesizer of claim 12, wherein each of the plurality of variable capacitor circuits are controlled by one of the control signals.

15. A method of operating a frequency synthesizer having a phase locked loop, comprising:

providing a plurality of parallel-connected continuously variable capacitor circuits within an LC tank resonant structure that together provide a capacitance amount that at least in part determines an output frequency for the frequency synthesizer;

generating a plurality of different control signals utilizing first and second clock signals, the first clock signal being generated from an output clock signal of the phase locked loop, the second clock signal being generated from a reference clock signal of the phase locked loop;

controlling the output frequency of a controllable oscillator of the phase locked loop by applying each of the plurality of control signals to at least different variable capacitor circuit to detemine at least in part the amount of capacitance that capacitor circuit contributes to the capacitance amount.

16. The method of operating a frequency synthesizer of claim 15, wherein the step of generating a plurality of signals further comprises the steps of:

generating a plurality of phase shifted signals utilizing the first clock signal;

detecting a phase difference between at least some of the phase shifted signals and the second clock signal; and

generating the plurality of control signals from the detected phase differences.

17. The method of operating a frequency synthesizer of claim 16, wherein at least five control signals are generated, each being connected to at least one different variable capacitor circuit.

18. The method of operating a frequency synthesizer of claim 15, wherein the step of generating a plurality of control signals further comprises the steps of:

generating a master control signal based on the first and second clock signals; and

generating the plurality of control signals from the master control signal.

19. The method of operating a frequency synthesizer of claim 15, wherein at least five control signals are generated, each being connected to at least one different variable capacitor circuit.

20. The method of operating a frequency synthesizer of claim 15, wherein at least twenty control signals are generated, each being connected to at least one different variable capacitor circuit.

21. The method of operating a frequency synthesizer of claim 15, wherein the step of providing the controllable oscillator with a plurality of variable capacitor circuits further comprises the steps of providing a first capacitor and a second capacitor coupled in series between the two common nodes, a third node being located between the first and second capacitors, and providing a variable resistance element configured to receive at least one of the control signals and being coupled to the third node and one of the common nodes.

34. The method of claim 15, further comprising providing the plurality of control signals from a sample and hold circuit.

22. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator, having an output frequency dependent upon a capacitance amount within an LC tank resonant structure;

a first clock node coupled to an output of the controllable oscillator;

a second clock node coupled to a reference clock;

a plurality of continuous analog control signals comprising at least five different analog control signals, the analog values of the analog control signals being generated at least in part from a phase difference between a first clock signal on the first clock node that is related to the output frequency and a second clock signal on the second clock node that is related to a reference frequency; and

a plurality of controllable oscillator inputs coupled to the analog control signals, the controllable oscillator inputs controlling at least in part the capacitance amount and thereby the output frequency of the controllable oscillator.

23. The frequency synthesizer of claim 22, further comprising a plurality of phase shifted signals, the phase shifted signals being generated from, at least in part, the first clock signal, and wherein the plurality of analog control signals are generated from a phase difference between at least some of the plurality of phase shifted signals and the second clock signal.

26. The frequency synthesizer of claim 22, further comprising:

a master control signal generator for generating a master control signal utilizing the first and second clock signals; and

a converter for converting the master control signal into the plurality of analog control signals.

27. The frequency synthesizer of claim 26, wherein the master control signal is indicative of the phase difference between the first and second clock signals.

24. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator, having an output frequency dependent upon a capacitance amount within an LC tank resonant structure;

a first clock node coupled to an output of the controllable oscillator;

a second clock node coupled to a reference clock;

a plurality of analog control signals comprising at least five different analog control signals, the analog values of the analog control signals being generated at least in part from a phase difference between a first clock signal on the first clock node that is related to the output frequency and a second clock signal on the second clock node that is related to a reference frequency;

a plurality of controllable oscillator inputs coupled to the analog control signals, the controllable oscillator inputs controlling at least in part the capacitance amount and thereby the output frequency of the controllable oscillator;

a plurality of phase shifted signals, the phase shifted signals being generated from, at least in part, the first clock signal, and wherein the plurality of analog control signals are generated from a phase difference between at least some of the plurality of phase shifted signals and the second clock signal; and

a shift register operatively coupled to the first clock node for generating the plurality of phase shifted signals.

25. The frequency synthesizer of claim 24, further comprising a phase detector connected between the shift register and the controllable oscillator for converting the plurality of phase shifted signals to the plurality of analog control signals.

28. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator, having an output frequency dependent upon a capacitance amount within an LC tank resonant structure, wherein the controllable oscillator comprises a plurality of parallel-connected continuously variable capacitor circuits for controlling the frequency of the controllable oscillator;

a first clock node coupled to an output of the controllable oscillator;

a second clock node coupled to a reference clock;

a plurality of analog control signals comprising at least five different analog control signals, the analog values of the analog control signals being generated at least in part from a phase difference between a first clock signal on the first clock node that is related to the output frequency and a second clock signal on the second clock node that is related to a reference frequency; and

a plurality of controllable oscillator inputs coupled to the analog control signals, the controllable oscillator inputs controlling the amount of capacitance contributed to the capacitance amount by the plurality of continuously variable capacitor circuits and thereby controlling the output frequency of the controllable oscillator.

29. A method of operating a frequency synthesizer having a phase locked loop, comprising:

generating a plurality of analog control voltages, the plurality comprising at least five different control voltages;

providing the plurality of different analog control voltages to inputs of a controllable oscillator;

controlling the output frequency of the oscillator with the plurality of analog control voltages, the output frequency being dependent upon a capacitance amount within an LC tank resonant structure; and

providing the controllable oscillator with a plurality of parallel-connected continuously variable capacitor circuits that together contribute at least part of the capacitance amount; and

controlling the plurality of variable capacitor circuits with the plurality of analog control voltages.

30. The method of operating a frequency synthesizer of claim 29, further comprising the step of detecting a phase difference between at least two signals within the phase locked loop, wherein the plurality of analog control voltages are generated from a result of the phase difference detection.

31. The method of operating a frequency synthesizer of claim 29, wherein the step of generating a plurality of analog control voltages further comprises the steps of:

generating a plurality of phase shifted signals utilizing a first clock signal within the phased locked loop;

detecting a phase difference between at least some of the phase shifted signals and a second clock signal within the phased locked loop; and

generating the plurality of analog control voltages from the detected phase differences.

32. The method of operating a frequency synthesizer of claim 29, wherein the step of generating a plurality of analog control voltages further comprises the steps of:

generating a master control signal based on first and second clock signals; and

generating the plurality of analog control voltages from the master control signal.