RISC CPU instructions particularly suited for decoding digital signal processing applications

• US 6,308,253 B1
• Filed: 03/31/1999
• Issued: 10/23/2001
• Est. Priority Date: 03/31/1999
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Khurshid, Mazin S., Gadre, Shirish
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/283,377
• Time in Patent Office: 937 Days
• Field of Search: 711/150, 711/153, 711/217, 711/219, 712/343, 712/41.23, 712/200, 712/26, 712/41, 712/224, 712/35, 712/223, 712/36, 712/37, 712/42, 712/341, 712/24, 712/25, 712/21, 712/22, 712/211, 712/213, 712/43, 712/20, 712/23, 707/101, 709/247, 709/322, 710/53
• US Class Current: 712/41
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: Y10S 707/99942 Manipulating data structure, e.g. compression, compaction, compilation

Abstract

A reduced programmable controller for an extensible digital signal processing architecture supports particular instructions to facilitate common digital signal processing operations. These instructions include extract and insert instructions, which are useful in managing the storage and extraction of digital signal processing variables to and from registers, and also useful in assembling fixed-length digital signal parameters from a section of a bitstream stored in a register. These instructions further include leading value detect instructions, including a leading zero detect instruction and a leading one detect instruction which are useful in parsing unique prefix codes such as Huffman codes used in MPEG encoding of video and other variable length codes, and useful in handling of a priority encoder such as a task manager.

Claims

1. An integrated circuit device circuit arrangement for processing multimedia data, the circuit arrangement comprising a processing core including:

(1) a datapath configured to perform a predetermined digital signal processing (DSP) operation;

(2) unit registers for storing data used in digital signal processing; and

(3) a programmable controller coupled to the datapath and unit registers, the programmable controller configured to execute a local computer program comprising instructions to control the operation of the datapath to process data, the programmable controller responding to an extract instruction identifying a source register of said unit registers, a target register of said unit registers, a number of bits and a starting position, by copying the identified number of bits, starting from the identified starting position, from the identified source register of said unit registers to a predetermined position in the identified target register of said unit registers.

2. The integrated circuit device of claim 1 wherein said predetermined position is a right justified position.

3. The integrated circuit device of claim 1 wherein said programmable controller further causes bits of the identified target register of said unit registers not copied from the identified source register of said unit registers to be reset to a predetermined value.

4. The integrated circuit device of claim 3 wherein said predetermined value is a zero value.

5. An integrated circuit device circuit arrangement for processing multimedia data, the circuit arrangement comprising a processing core including:

(1) a datapath configured to perform a predetermined digital signal processing (DSP) operation;

(2) unit registers for storing data used in digital signal processing; and

(3) a programmable controller coupled to the datapath and unit registers, the programmable controller configured to execute a local computer program comprising instructions to control the operation of the datapath to process data, the programmable controller responding to an insert instruction identifying a source register of said unit registers, a target register of said unit registers, a number of bits and a starting position, by copying the identified number of bits from the identified source register of said unit registers, starting from a predetermined position in the identified source register of said unit registers, to the identified target register of said unit registers, starting at the identified starting position.

6. The integrated circuit device of claim 5 wherein said predetermined position is a right justified position.

7. The integrated circuit device of claim 5 wherein bits of the identified target register of said unit registers not copied from the identified source register of said unit registers are not changed.

8. An integrated circuit device circuit arrangement for processing multimedia data, the circuit arrangement comprising a processing core including:

(1) a datapath configured to perform a predetermined digital signal processing (DSP) operation;

(2) unit registers for storing data used in digital signal processing; and

(3) a programmable controller coupled to the datapath and unit registers, the programmable controller configured to execute a local computer program comprising instructions to control the operation of the datapath to process data, the programmable controller responding to a leading value detect instruction identifying a target register of said unit registers and a destination register of said unit registers, by identifying the position of a bit closest to a predetermined end of the identified target register of said unit registers which has a predetermined binary value, and writing an indication of the identified position into the identified destination register of said unit registers.

9. The integrated circuit device of claim 8 wherein said leading value detect instruction is a leading zero detect instruction, and said predetermined binary value is 0.

10. The integrated circuit device of claim 9 wherein said predetermined end of the identified target register of said unit registers is a most significant end.

11. The integrated circuit device of claim 8 wherein said leading value detect instruction is a leading one detect instruction, and said predetermined binary value is 1.

12. The integrated circuit device of claim 11 wherein said predetermined end of the identified target register of said unit registers is a most significant end.

13. The integrated circuit device of claim 8 wherein the identified position is written as a binary number into the identified destination register of said unit registers.

14. The integrated circuit device of claim 13 wherein the binary number is written at a least significant end of the identified destination register of said unit registers, and all other bits of the identified destination register of said unit registers are cleared.