System for synchronizing discrete components to a common clock source

• US 6,308,280 B1
• Filed: 06/25/1998
• Issued: 10/23/2001
• Est. Priority Date: 06/25/1998
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Original Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Inventors: Joseph, Kuriacose, Casavant, Scott
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US09/104,466
• Time in Patent Office: 1,216 Days
• Field of Search: 713/400, 713/500, 713/502, 713/503, 713/600, 709/400
• US Class Current: 713/400
• CPC Class Codes: H04H 40/90 specially adapted for satellite broadcast receiving
• CPC Class Codes: H04N 21/4143 embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/4302 Content synchronisation processes, e.g. decoder synchronisation
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/6143 involving transmission via a satellite

Abstract

A method and apparatus for synchronizing downstream circuit boards with the clock values transmitted in the incoming bitstream of a digital broadcast data signal from a digital satellite system (DSS) or digital video broadcast (DVB) is disclosed. The disclosed embodiments use the generation of quasi-periodic interrupts which latch, at the same time for all downstream circuits, local clock times. The differences between successive local clock times are compared in downstream processors to differences between a front-end circuits locked system times to determine local clock adjustment values to synchronize downstream circuits.

Claims

1. A method of synchronizing a plurality of computer subsystems to a transmitted clock in an incoming bitstream, wherein each subsystem comprises a local clock, the method comprising the steps of:

locking said local clock of a front-end computer subsystem with said transmitted clock received in said incoming bitstream; and

recording a plurality of quasi-periodic local times on said front-end computer subsystem and on each one of said plurality of downstream computer subsystems; and

comparing each one of a plurality of quasi-periodic local times of said front-end computer subsystem with each one of said plurality of quasi-periodic local times of said plurality of downstream computer subsystems to determine synchronization; and

adjusting said local clocks of each one of said plurality of downstream computer subsystems.

2. The method of claim 1, wherein the step of recording said plurality of local times on said front-end computer subsystem and on each one of said plurality of downstream computer subsystems includes generating a plurality of quasi-periodic interrupts, wherein said quasi-periodic interrupts are generated within the computer system.

3. The method of claim 2 wherein said quasi-periodic interrupts are derived from a bus clock of an associated computer.

4. The method of claim 1, wherein the step of recording said plurality of local times includes sending each one of a plurality of quasi-periodic interrupts to said front-end computer subsystem and each one of said plurality of downstream computer subsystems to be synchronized, wherein said quasi-periodic interrupts arrive at the same time to said recording means of each one of said plurality of computer subsystems.

5. The method of claim 1, wherein the step of recording said plurality of local times includes storing said local time at the receipt of each one of a plurality of quasi-periodic interrupts, wherein there is a separate storage means for said front-end computer subsystem and for each one of said plurality of downstream computer subsystems.

6. The method of claim 1, wherein the step of comparing said local times of said front-end computer subsystem with said local times of said plurality of downstream computer subsystems includes computing a plurality of system times from said local times for said front-end computer subsystem, wherein each said system time corresponds to said local time plus an offset.

7. The method of claim 6, wherein the step of comparing said system time to said local times includes transmitting said system time value of said front-end computer subsystem and said local time values of each one of said plurality of downstream computer subsystems to a processing means.

8. The method of claim 1, wherein the step of comparing comprises comparing changes in system time between quasi-periodic interrupts to changes in said local times between quasi-periodic interrupts.

9. The method of claim 1, wherein the step of comparing comprises determining, for each quasi-periodic interrupt, if each one of said local clocks of said plurality of downstream computer subsystems is synchronized to said front-end computer subsystem'"'"'s local clock.

10. The method of claim 1, wherein the step of adjusting said local clocks of each unsynchronized one of said plurality of downstream computer subsystems is carried out by a processor having a control feedback loop, whereby synchronization instructions are sent from said processor to controls that drive each local clock of said plurality of downstream computer subsystems.

11. An apparatus for synchronizing a plurality of downstream computer subsystems to a transmitted clock of an incoming bitstream, wherein each one of said plurality of downstream computer subsystems comprises at least one clocking means for measuring a plurality of local timing values, said apparatus comprising:

a computer comprising a motherboard, wherein a frontend computer subsystem and said plurality of downstream computer subsystems are connected to said motherboard;

a front-end computer subsystem, wherein said front-end computer subsystem comprises a local clock and means to lock said local clock to said transmitted clock of said incoming bitstream;

means for generating a plurality of quasi-periodic interrupts;

means for transmitting said plurality of quasi-periodic interrupts to said front-end computer subsystem and to said plurality of downstream computer subsystems, wherein each one of said plurality of quasi-periodic interrupts arrives to said front-end computer subsystem and to each one of said plurality of downstream computer subsystems at the same time;

means for storing a local time on said front-end computer subsystem and each one of said plurality of downstream computer subsystems, wherein said local time corresponds to each one of said plurality of quasi-periodic source interrupts;

means for comparing the difference between successive values of a plurality of system times of said front-end computer subsystem with the difference between successive values of a plurality of quasi-periodic local times of said plurality of downstream computer subsystems; and

means for adjusting said local clocks of each unsynchronized one of said plurality of downstream computer subsystems.

12. The apparatus of claim 11, wherein said front-end computer subsystem and each one of said plurality of downstream computer subsystems comprise at least one of said storing means coupled with said clocking means for storing said plurality of said local timing values.

13. The apparatus of claim 11, wherein said clocking means and said storing means of each one of said plurality of downstream computer subsystems are controlled by at least one processing means.

14. The apparatus of claim 11, wherein means for generating a plurality of quasi-periodic source interrupts comprises a counter residing on said computer motherboard.

15. The apparatus of claim 11, wherein means for transmitting said plurality of quasi-periodic source interrupts to said plurality of downstream computer subsystems comprises a backbone bus, wherein said backbone bus is connected to said storing means, to processing means associated with each one of said plurality of downstream computer subsystems, and to said generating means creating said quasi-periodic interrupts.

16. The apparatus of claim 11, wherein said means for storing said local time on each said plurality of downstream computer subsystems comprises a plurality of interrupt triggered latches, wherein each latch is associated with no more than one of said plurality of downstream computer subsystems.