Method and system for environmental sensing and control within a computer system

• US 6,308,289 B1
• Filed: 10/01/1998
• Issued: 10/23/2001
• Est. Priority Date: 10/01/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Duron, Mike Conrad, Faust, Robert Allan, McLaughlin, Charles Andrew, Shempert, Craig Henry, Ahrens, George Henry, Szabo, Kurt Paul
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): Bonzo, Bryce P.
• Application Number:
  US09/165,161
• Time in Patent Office: 1,118 Days
• Field of Search: 702/59, 702/153, 236/94, 374/152, 361/103, 710/48, 710/49, 710/50, 710/262, 714/47, 714/48
• US Class Current: 714/48
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206

Abstract

In accordance with the method and system of the present invention, a local processor utilizes registers arranged in a fault/mask/cache fashion for environmental control and sensing within a data processing system. The local processor continuously reads input data from a variety of environmental sensors in order to determine if a threshold level has been reached and a fault condition exists. Cache registers allow the local processor to store/pass detailed sensor information to system firmware within system processor(s). The local processor sets a fault bit within a fault register designed to cause an interrupt to the system level firmware if any of its bits are non-zero, indicating that a fault condition has occurred. A mask register is designed to allow the interaction of both the local processor and system processor(s) when an interrupt is being serviced and help keeps track of which interrupts are being serviced and which are yet to be serviced in the case of multiple interrupt sources. The system firmware will service the interrupt and set the mask bit. The action will signal the local processor that the system has acknowledged the interrupt and will take the appropriate action. The local processor may now post another fault, exactly like the first fault, by clearing the mask bit and causing a subsequent interrupt to the system. The fault, mask, cache, and both local and system processor(s) work together to provide a positive interlock for synchronizing their actions with each other.

Claims

1. A method of environmental sensing and control for one or more devices having associated sensors within a computer system, comprising the steps of:

receiving, by a local processor, environmental sensor inputs from one or more devices through associated one or more sensors;

writing said environmental sensor inputs into a register on said local processor;

determining if a threshold level has been crossed from said associated one or more sensors;

responsive to determining that one or more threshold levels have been crossed, determining if a fault condition exists for said one or more devices;

responsive to determining that one or more fault conditions exists, said local processor checking one or more bits for causing an interrupt for servicing said one or more fault conditions by one or more system processors; and

responsive to determining that said one or more fault conditions no longer exist, resetting said one or more bits.

2. The method of claim 1, wherein said register is a cache register.

3. The method of claim 1, wherein said checking one or more bits includes checking one or more fault bits and one or more mask bits.

4. The method of claim 3, further comprising:

responsive to checking said one or more fault bits, setting said one or more fault bits to corresponding said one or more fault conditions for causing said interrupt.

5. The method of claim 4, further comprising:

responsive to checking said one or more mask bits, resetting said one or more mask bits to corresponding said one or more fault conditions for causing said interrupt.

6. The method of claim 4, further comprising:

responsive to checking said one or more mask bits, scanning said sensors by said local processor when said one or more mask bits are not set to corresponding said one or more fault bits that are set.

7. The method of claim 3, further comprising:

reading said one or more fault bits and corresponding said cache register values by said system processors for servicing said one or more fault conditions.

8. The method of claim 7, further comprising:

shutting down a computer system by said system processors when a critical environmental condition is indicated by said cache register values.

9. The method of claim 7, further comprising:

logging an entry for deferred maintenance for a computer sub-system by said system processors when an environmental warning condition is indicated by said cache register values.

10. The method of claim 7, further comprising:

setting said one or more mask bits to corresponding said one or more fault bits by said system processors after servicing said one or more fault conditions.

11. An information handling system, comprising:

means for receiving, by a local processor, environmental sensor inputs from one or more devices through associated one or more sensors;

means for writing said environmental sensor inputs into a register on said local processor;

means for determining if one or moret threshold levels have been crossed from said associated one or more sensors;

means for determining if one or more fault conditions exists for said one or more threshold levels;

means for checking said one or more bits by said local processor for causing an interrupt for servicing said one or more fault conditions by one or more system processors; and

means for resetting said one or more bits when said one or more fault conditions no longer exist.

12. An information handling system according to claim 11, wherein said register is a cache register.

13. An information handling system according to claim 11, wherein said means for checking one or more bits includes means for checking one or more fault bits and one or more mask bits.

14. An information handling system according to claim 13, further comprising:

means for setting said one or more fault bits to corresponding said one or more fault conditions for causing said interrupt.

15. An information handling system according to claim 14, further comprising:

means for resetting said one or more mask bits to corresponding said one or more fault conditions for causing said interrupt.

16. An information handling system according to claim 14, further comprising:

means for determining when said one or more mask bits are not set to corresponding said one or more fault bits that are set for scanning said sensors by said local processor.

17. An information handling system according to claim 13, further comprising:

means for reading said one or more fault bits and corresponding said cache register values by said system processors for servicing said one or more fault conditions.

18. An information handling system according to claim 17, further comprising:

means for shutting down a computer system by said system processors when a critical environmental condition is indicated by said cache register values.

19. An information handling system according to claim 17, further comprising:

means for logging an entry for deferred maintenance for a computer sub-system by said system processors when an environmental warning condition is indicated by said cache register values.

20. An information handling system according to claim 17, further comprising:

means for setting said one or more mask bits to corresponding said one or more fault bits by said system processors after servicing said one or more fault conditions.

21. A computer program product residing on a computer usable medium for providing environmental control and sensing to an information handling system, comprising:

instruction means for receiving, by a local processor, environmental sensor inputs from one or more devices through associated one or more sensors;

writing said environmental sensor inputs into said cache register;

instruction means for determining if one or more threshold levels have been crossed from said associated one or more sensors;

instruction means for determining if one or more fault conditions exists for said one or more threshold levels;

instruction means for checking one or more bits by said local processor for causing an interrupt for servicing said one or more fault conditions by one or more system processors; and

instruction means for resetting said one or more bits when said one or more fault conditions no longer exist.