Method for testing an electronic circuit

• US 6,308,291 B1
• Filed: 09/18/1998
• Issued: 10/23/2001
• Est. Priority Date: 09/18/1997
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Schneider, Peter, Kock, Ernst-Josef
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US09/156,442
• Time in Patent Office: 1,131 Days
• Field of Search: 714/724, 714/726, 714/729, 714/736
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts

Abstract

A method for testing an electronic circuit is described, in which the actual state of circuit components which have previously been activated on a test basis after an initial initialization is compared with a setpoint state. Of the circuit components to be tested, essentially only those circuit components are operated simultaneously which, under the given circumstances, can be expected to interact in the context.

Claims

1. A method of testing an electronic circuit, which comprises:

initializing a number of circuit components;

simultaneously activating essentially only those circuit components on a test basis of which interaction is expected in a given context; and

reading out an actual state of the circuit components to be tested, and comparing the actual state of the circuit components with a setpoint state.

2. The method according to claim 1, wherein the circuit to be tested comprises a plurality of flip-flops and the method further comprises using at least some of the flip-flops of the circuit as scan chain elements.

3. The method according to claim 1, which comprises using a specific test clock signal as clock signal for initializing, for actuating on a test basis, and for reading out the states of the circuit to be tested.

4. The method according to claim 1, which comprises defining circuit components to be selectively activated and deactivated in each case all elements of one or more scan chains.

5. The method according to claim 1, which comprises defining selected components of one or more scan chains as circuit components to be selectively activated and deactivated.

6. The method according to claim 1, which comprises repeating the initializing, activating, and reading steps during a plurality of test runs and at least partly activating different circuit components during each test run.

7. The method according to claim 6, which comprises defining a number of test runs such that ultimately each of the circuit components to be tested has been activated at least once alone or together with other circuit components.

8. The method according to claim 7, which comprises placing all circuit components to be tested into identical initial states before each test run.

9. The method according to claim 1, which comprises changing the contents of the register as a function of circuit-specific presettings and a number of a respective test run.

10. A method of testing an electronic circuit, which comprises:

initializing a number of circuit components;

in the initialization step, placing a circuit to be tested in a scan mode of operation in which elements whose state is to be initialized and read out are connected one behind the other to form one or more scan chains;

assigning elements to various scan chains and defining a sequence within a given scan chain such that clock signals with which the scan chain elements are clocked reach the scan chain elements during the activating step no later than at a time at which signals are to be one of received and transmitted by the respective scan chain element;

simultaneously activating essentially only those circuit components on a test basis of which interaction is expected in a given context; and

reading out an actual state of the circuit components to be tested, and comparing the actual state of the circuit components with a setpoint state.

11. A method of testing an electronic circuit, which comprises:

initializing a number of circuit components;

simultaneously activating essentially only those circuit components on a test basis of which interaction is expected in a given context;

reading out an actual state of the circuit components to be tested, and comparing the actual state of the circuit components with a setpoint state; and

supplying no clock signals to those parts of the circuit which, at the time, are not to be initialized, activated on a test basis, or read out.

12. A method of testing an electronic circuit, which comprises:

initializing a number of circuit components;

simultaneously activating essentially only those circuit components on a test basis of which interaction is expected in a given context;

reading out an actual state of the circuit components to be tested, and comparing the actual state of the circuit components with a setpoint state; and

assigning registers to given circuit components, and making an application of a normal clock signal, a test clock signal, or no clock signal to said given circuit components dependent on contents of the given registers assigned to the circuit components and on a status of a mode-of-operation-selection signal.