Method for reconfiguring a field programmable gate array from a host
First Claim
1. A method of reconfiguring an FPGA interface device including a microcontroller and an on-board FPGA having a serial data port coupled to a non-volatile memory and a parallel data port coupled to a volatile memory, the method comprising the steps of:
- storing a default configuration design for the on-board FPGA in the non-volatile memory;
booting up the FPGA interface device, whereby the on-board FPGA is in a serial configuration mode such that the on-board FPGA is configured using the default configuration design;
downloading a new configuration design to the interface device via the microcontroller;
storing the new configuration design in the volatile memory; and
reconfiguring the on-board FPGA using the new configuration design read from the volatile memory via the parallel port.
1 Assignment
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Accused Products
Abstract
A method is disclosed for reconfiguring an on-board FPGA of an interface device without resetting the interface device. The FPGA interface device also includes a microcontroller, and the on-board FPGA has a serial data port coupled to a first, non-volatile memory and a parallel data port coupled to a second memory, which may be a volatile memory. The default configuration design is stored in the non-volatile memory. The on-board FPGA is initially in a serial configuration mode such that upon power-up, the on-board FPGA looks to the first memory via its serial port for the configuration design. Where it is desired to reconfigure the on-board FPGA, a new configuration design is stored in the second memory, and the on-board FPGA is instructed to reconfigure itself in parallel mode. In response thereto, the on-board FPGA looks to the second memory via its parallel port, retrieves the new configuration design, and then reconfigures itself accordingly.
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Citations
6 Claims
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1. A method of reconfiguring an FPGA interface device including a microcontroller and an on-board FPGA having a serial data port coupled to a non-volatile memory and a parallel data port coupled to a volatile memory, the method comprising the steps of:
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storing a default configuration design for the on-board FPGA in the non-volatile memory;
booting up the FPGA interface device, whereby the on-board FPGA is in a serial configuration mode such that the on-board FPGA is configured using the default configuration design;
downloading a new configuration design to the interface device via the microcontroller;
storing the new configuration design in the volatile memory; and
reconfiguring the on-board FPGA using the new configuration design read from the volatile memory via the parallel port. - View Dependent Claims (2, 3, 4, 5, 6)
switching the on-board FPGA to a parallel configuration mode;
reading the new configuration design from the parallel port, rather than reading the default configuration design from the serial port, in response to the switching step; and
reconfiguring the on-board FPGA according to the new configuration design.
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5. The method of claim 4, wherein the switching step further comprises toggling a configuration mode pin of the on-board FPGA.
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6. The method of claim 5, wherein the on-board FPGA toggles its configuration mode pin.
Specification