Method for synthesis of common-case optimized circuits to improve performance and power dissipation

• US 6,308,313 B1
• Filed: 06/09/1999
• Issued: 10/23/2001
• Est. Priority Date: 06/09/1999
• Status: Expired due to Term

• Current Assignee: NEC Corporation, Princeton University
• Original Assignee: NEC Corporation
• Inventors: Khouri, Kamal S., Lakshminarayana, Ganesh, Raghunathan, Anand, Jha, Niraj K.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US09/328,897
• Time in Patent Office: 867 Days
• Field of Search: 716/18, 716/2, 716/3
• US Class Current: 716/104
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A method for designing a circuit with reduced power consumption using a Common-Case Computation (CCC) based design. The method comprising identifying a set of common case computations from a schedule of the circuit, designing add on common detection circuit that detects the set of common case computations, designing add on common case execution circuit that executes the set of common case computations; and integrating the add on circuitry with the original circuit. A circuit design system for optimizing a circuit for power management comprising: a simulator for simulating a schedule with input traces based on a given RTL design, schedule and typical input traces; a state sequence identifier for identifying promising state sequence patterns from simulated schedules; a behavior extractor for extracting behavior corresponding to each identified state sequences; a pattern selector for choosing a best pattern; a synthesizer for synthesizing common case circuitry; and an output generator for integrating common case circuitry with an original circuit.

Claims

1. A method of designing a circuit with reduced power consumption, said method comprising:

identifying a set of common case computations from a schedule of the circuit;

designing add on common case detection circuit that detects the set of common case computations;

designing add on common case execution circuit that executes the set of common case computations; and

integrating the add on circuitry with the circuit.

2. A method of optimizing a circuit for reducing power consumption in the circuit comprising:

a) simulating a schedule with input traces based on an RTL design, schedule and typical input traces;

b) identifying promising state sequence patterns from the result of step a;

c) extracting behavior corresponding to each state sequences identified in step b;

d) choosing a best pattern;

e) synthesizing common case circuitry, wherein the common case circuitry implements the best pattern; and

f) integrating the synthesized common case circuitry with original circuit.

3. The method of claim 2 wherein step c comprises:

(c) (i) deriving compact justification behavior;

(c)(ii) optimizing computation performed in state sequence; and

(c)(iii) evaluating power savings obtained by choosing a selected patter.

4. The method of claim 2 wherein promising state sequences are identified based on a length and coverage of a common case.

5. The method of claim 4 wherein promising state sequences are identified using a parameter:

6. The method of claim 5 wherein some infrequent occurrences of the common case are ignored.

7. The method of claim 5 wherein some hard-to-detect occurrences of the common case are ignored.

8. The method of claim 2 wherein an occurrence of a state sequence representing a common case σ

={S₁, S₂ . . . S_n}, is detected using a variable X, the value of X being obtained by performing an AND operation on c_i, where c_i represents a transition from S_i to S_i+1.

9. A circuit design system for optimizing a circuit for reducing power consumption in the circuit comprising:

a simulator for simulating a schedule with input traces based on a given RTL design, schedule and typical input traces;

a state sequence identifier for identifying promising state sequence patterns from simulated schedules;

a behavior extractor for extracting behavior corresponding to each identified state sequences;

a pattern selector for choosing a best pattern;

a synthesizer for synthesizing common case circuitry, wherein the common case circuitry implements the best pattern; and

an output generator for integrating the synthesized common case circuitry with an original circuit.