Manufacturable GaAs VFET process

• US 6,309,918 B1
• Filed: 09/21/1998
• Issued: 10/30/2001
• Est. Priority Date: 09/21/1998
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gable, Benjamin W., Eisenbeiser, Kurt, Huang, Jenn-Hwa, Rhine, David
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US09/157,430
• Time in Patent Office: 1,135 Days
• Field of Search: 438/138, 438/570, 438/173, 438/176, 438/186, 438/192, 438/135, 438/136, 438/137, 438/268, 438/270, 438/576, 438/571, 438/167, 438/720, 438/742, 438/945
• US Class Current: 438/173
• CPC Class Codes: H01L 29/66856 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/8122 Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: Y10S 438/945 Special, e.g. metal

Abstract

A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.

Claims

1. A manufacturable GaAs VFET process comprising the steps of:

providing a substrate structure including a doped GaAs supporting substrate, a lightly doped first epitaxial layer including GaAs positioned on a first surface of the supporting substrate, and a heavily doped second epitaxial layer including GaAs positioned on the first epitaxial layer;

depositing a temperature tolerant conductive layer on the second epitaxial layer;

patterning the conductive layer to define a plurality of source areas underlying portions of patterned conductive layer;

using the portions of patterned conductive layer, etching a plurality of gate trenches into the first epitaxial layer of the substrate structure adjacent the source areas, the gate trenches having bottoms spaced vertically from the second epitaxial layer;

implanting material in the bottoms of the gate trenches to form implanted gate areas in the gate trenches and activating the implanted gate areas;

depositing a gate contact in communication with the implanted gate areas by depositing a thin metal layer on the implanted gate areas to reduce gate resistance wherein the step of etching the plurality of gate trenches included undercutting the portions of patterned conductive layer to prevent metal from being deposited on trench sides during the step of depositing the thin metal layer on the implanted gate areas;

depositing a source contact in communication with the portions of patterned conductive layer overlying the source areas; and

depositing a drain contact on a second surface of the substrate structure.

2. A manufacturable GaAs VFET process as claimed in claim 1 wherein the step of providing the substrate structure includes providing a supporting substrate of N+ GaAs, a first epitaxial layer of N−

GaAs, and a second epitaxial layer of N++ InGaAs.

3. A manufacturable GaAs VFET process as claimed in claim 2 wherein the step of implanting material in the bottoms of the gate trenches includes implanting one of argon and carbon ions to form p conductivity implanted gate areas.

4. A manufacturable GaAs VFET process as claimed in claim 1 wherein the step of depositing the temperature tolerant conductive layer includes depositing a layer of conductive material which remains a layer during activation of the implanted gate areas.

5. A manufacturable GaAs VFET process as claimed in claim 4 wherein the step of depositing the layer of conductive material includes depositing one of a refractory metal, a metal silicide, a metal nitride, and a metal oxide.

6. A manufacturable GaAs VFET process as claimed in claim 1 wherein the step of patterning the conductive layer to define the plurality of source areas includes forming a pattern of photoresist on the layer of conductive material defining the source areas, and etching the layer of conductive material using the layer of photoresist as a mask to form the source areas.

7. A manufacturable GaAs VFET process as claimed in claim 1 wherein the step of etching the layer of conductive material includes reactive ion etching the conductive layer.

8. A manufacturable GaAs VFET process as claimed in claim 1 wherein the step of etching the plurality of gate trenches includes using a GaAs etch including chlorine chemistry to etch the substrate structure.

9. A manufacturable GaAs VFET process as claimed in claim 1 wherein the step of providing the substrate structure includes providing a substrate structure having a first conductivity and the step of implanting material in the bottoms of the gate trenches to form implanted gate areas includes forming implanted gate areas of a second conductivity opposite to the first conductivity.

10. A manufacturable GaAs VFET process as claimed in claim 1 including in addition a step of probing the VFET to determine implant resistivity and gate-to-source leakage subsequent to the step of depositing the gate contact.

11. A manufacturable GaAs VFET process as claimed in claim 1 wherein the step of depositing the gate contact includes depositing ohmic metal on an implanted area in communication with and remote from the implanted gate areas in the bottoms of the gate trenches.

12. A manufacturable GaAs VFET process as claimed in claim 1 wherein the step of depositing the source contact in communication with the portions of patterned conductive layer overlying the source areas includes filing the gate trenches with an insulating material so as to leave the portions of patterned conductive layer overlying the source areas exposed, and depositing a layer of source contact metal over the insulating material and in electrical contact with the portions of patterned conductive layer.

13. A manufacturable GaAs VFET process comprising the steps of:

providing a substrate structure including a doped GaAs supporting substrate, a lightly doped first epitaxial layer including GaAs positioned on a first surface of the supporting substrate, and a heavily doped second epitaxial layer including GaAs positioned on the first epitaxial layer;

depositing a temperature tolerant conductive layer on the second epitaxial layer where the temperature tolerance is such that the layer of conductive material remains a layer during annealing for activation of implanted areas;

pattering the conductive layer to define a plurality of spaced apart, elongated source areas underlying portions of patterned conductive layer;

using the portions of patterned conductive layer, etching a plurality of gate trenches into the first epitaxial layer of the substrate structure adjacent the source areas so as to form elongated raised fingers between the gate trenches with the elongated source areas underlying portions of patterned conductive layer on an upper surface of the raised fingers, the gate trenches having bottoms spaced vertically from the second epitaxial layer, and the plurality of gate trenches being interconnected;

implanting material in the first epitaxial layer at the bottoms of the gate trenches to form implanted gate areas in the gate trenches;

annealing to activate the implanted gate areas;

depositing a gate contact in communication with the implanted gate areas by depositing a thin metal layer on the implanted gate areas to reduce gate resistance wherein the step of etching the plurality of gate trenches included undercutting the portions of patterned conductive layer to prevent metal from being deposited on trench sides during the step of depositing the thin metal layer on the implanted gate areas;

depositing a source contact in communication with the portions of patterned conductive layer overlying the source areas; and

depositing a drain contact on a second surface of the substrate structure.

14. A manufacturable GaAs VFET process as claimed in claim 13 wherein the step of providing the substrate structure includes providing a supporting substrate of N+ GaAs, a first epitaxial layer of N−

GaAs, and a second epitaxial layer of N++ InGaAs.

15. A manufacturable GaAs VFET process as claimed in claim 14 wherein the step of implanting material in the bottoms of the gate trenches includes implanting one of argon and carbon ions to form p conductivity implanted gate areas.

16. A manufacturable GaAs VFET process as claimed in claim 13 wherein the step of depositing the layer of temperature tolerant conductive material includes depositing one of a refractory metal, a metal silicide, a metal nitride, and a metal oxide.

17. A manufacturable GaAs VFET process as claimed in claim 13 wherein the step of etching the plurality of gate trenches includes using a GaAs etch including chlorine chemistry to etch the substrate structure.

18. A manufacturable GaAs VFET process as claimed in claim 13 including in addition a step of probing the VFET to determine implant resistivity and gate-to-source leakage subsequent to the step of depositing the gate contact.