Bipolar transistor which can be controlled by field effect and method for producing the same

• US 6,309,920 B1
• Filed: 04/10/2000
• Issued: 10/30/2001
• Est. Priority Date: 07/22/1997
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Tihanyi, Jenoe, Auerbach, Franz, Porst, Alfred, Laska, Thomas, Miller, Gerhard, Brunner, Heinrich
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US09/462,760
• Time in Patent Office: 568 Days
• Field of Search: 438/202, 438/206, 438/268, 438/315, 438/338, 438/342, 438/350, 257/263
• US Class Current: 438/202
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

A method for forming a field effect vertical bipolar transistor that includes a semiconductive body that has at its top surface a plurality of emitter zones of one conductivity type, each surrounded by a base zone of the opposite conductivity type, and gate electrodes for creating a channel at the surface through the base zone into the bulk inner portion of the one conduction type and at a bottom surface a collector zone that includes a collector electrode overlying a collector layer of the opposite conduction type overlying a field stop layer heavily doped of the opposite conduction type overlying the inner portion lightly doped of the one conduction type. Each of the collector layer and the field stop layer is less than 2 microns in thickness and the collector layer is used to inject minority carriers into the inner zone when appropriately biased.

Claims

1. The method of forming an insulated gate bipolar transistor comprising the steps of:

forming, at the top surface of a semiconductive substrate that is doped to be of one conductivity type for serving as the inner zone of the transistor, at least one emitter zone of the one conductivity type with each emitter enclosed within a separate base zone of the opposite conductivity type;

forming, at the top surface of the semiconductive substrate, a plurality of gate electrodes for inducing channels at the top surface of the substrate for the flow of charge carriers between the emitter zones and the bulk of the substrate by way of the base zones;

forming, at the bottom surface of the substrate, a polycrystalline field stop zone layer of the one conductivity type but more heavily doped than the bulk of the substrate;

and forming, at the surface of the field stop layer a collector layer and a collector electrode for injecting minority carriers into the bulk of the substrate, the doping in the collector layer being higher than in the field stop zone layer and of the opposite conductivity type.

2. The method of claim 1 in which neither the field stop zone layer nor the collector layer is thicker than 2 microns nor less than the thickness of the inner zone of the transistor.

3. The method of claim 2 in which the collector layer and the collector electrode are formed by a Schottky contact to said bottom surface of the substrate.

4. The method of claim 3 in which the gate electrodes are formed as doped polysilicon layers separated from the top surface of the substrate by an oxide layer.

5. The method of claim 1 in which the gate electrodes are formed as doped polysilicon layers separated from the top surface of the substrate by an oxide layer.