Method for fabrication of on-chip inductors and related structure

• US 6,309,922 B1
• Filed: 07/28/2000
• Issued: 10/30/2001
• Est. Priority Date: 07/28/2000
• Status: Expired due to Term

• Current Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Liu, Q. Z., Zhao, Bin, Howard, David
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US09/627,505
• Time in Patent Office: 459 Days
• Field of Search: 438/238, 438/381, 438/130, 438/619, 438/766, 438/783
• US Class Current: 438/238
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors

Abstract

Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

Claims

1. A method comprising steps of:

covering a first semiconductor die area, said first semiconductor die area including a first dielectric area, said first dielectric area having a first permeability;

interspersing a permeability conversion material in a second area of said semiconductor die, said second semiconductor die area including a second dielectric area, said permeability conversion material having a second permeability, said second permeability being higher than said first permeability.

2. The method of claim 1 wherein said covering step comprises covering said first semiconductor die area with photoresist.

3. The method of claim 1 wherein said first dielectric area comprises silicon dioxide.

4. The method of claim 1 wherein said first dielectric area comprises a low-k dielectric.

5. The method of claim 1 wherein said second dielectric area comprises silicon dioxide.

6. The method of claim 1 wherein said second dielectric area comprises a low-k dielectric.

7. The method of claim 1 wherein said permeability conversion material is selected from the group comprising of nickel, iron, nickel-iron alloy, and magnetic oxide.

8. The method of claim 1 wherein said step of interspersing is performed by implanting said permeability conversion material in said second area of said semiconductor die.

9. The method of claim 1 wherein said step of interspersing is performed by sputtering said permeability conversion material on said second area of said semiconductor die.

10. The method of claim 1 further comprising a step of patterning a conductor within said second dielectric area, said conductor forming an inductor.

11. The method of claim 10 wherein said conductor is selected from the group consisting of copper, aluminum, and copper-aluminum alloy.

12. The method of claim 10 wherein said conductor is patterned as a square spiral.

13. The method of claim 10 wherein said permeability conversion material is selected from the group comprising of nickel, iron, nickel-iron alloy, and magnetic oxide.

14. The method of claim 10 wherein said step of interspersing is performed by implanting said permeability conversion material in said second area of said semiconductor die.

15. The method of claim 10 wherein said step of interspersing is performed by sputtering said permeability conversion material on said second area of said semiconductor die.

16. A method comprising steps of:

patterning a conductor within a dielectric;

interspersing a permeability conversion material in said dielectric, wherein said permeability conversion material has a permeability greater than a permeability of said dielectric.

17. The method of claim 16 wherein said dielectric comprises silicon dioxide.

18. The method of claim 16 wherein said dielectric comprises a low-k dielectric.

19. The method of claim 16 wherein said permeability conversion material is selected from the group comprising of nickel, iron, nickel-iron alloy, and magnetic oxide.

20. The method of claim 16 wherein said step of interspersing is performed by implanting said permeability conversion material in said dielectric.

21. The method of claim 16 wherein said step of interspersing is performed by sputtering said permeability conversion material on said dielectric.

22. The method of claim 16 wherein said conductor is selected from the group consisting of copper, aluminum, and copper-aluminum alloy.

23. The method of claim 16 wherein said conductor is patterned as a square spiral.