Method of forming trench MOS device and termination structure

• US 6,309,929 B1
• Filed: 09/22/2000
• Issued: 10/30/2001
• Est. Priority Date: 09/22/2000
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute, General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: Industrial Technology Research Institute and Genetal Semiconductor of Taiwan Limited
• Inventors: Tsai, Ming-Jinn, Hsu, Chih-Wei, Kung, Pu-Ju, Liu, Chung-Min, Kao, Ming-Che
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/668,906
• Time in Patent Office: 403 Days
• Field of Search: 438/270, 438/361, 438/425, 438/430, 438/589, 251/496
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped. Thereafter, a termination structure oxide layer is formed through deposition, lithographic process and etching. After backside unnecessary layers removal, a sputtering metal layers deposition, lithographic process and etching step are successively performed to form the first electrode with a desired ended location and the second electrode on both side of semiconductor substrate.

Claims

1. A method of fabricating trench MOS devices and termination structure simultaneously, said method comprising the steps of:

providing a semiconductor substrate;

forming a plurality of first trenches for forming said trench MOS devices in an active region of a semiconductor substrate, and a second trench for forming said termination structure from a boundary of said active region to a margin of said semiconductor substrate, said second trench and said first trench spaced by a mesa;

performing a thermal oxidation process so as to form a gate oxide on all areas of said semiconductor substrate;

refilling said plurality of first trenches and said second trench with a first conductive material;

performing an etching back process using a surface of said semiconductor substrate of said mesa as a stopping layer, and forming a spacer on a sidewall of said second trench;

removing said gate oxide layer using said surface of said semiconductor substrate of said mesa as a stopping layer;

forming a termination structure oxide layer on all areas of said semiconductor substrate;

forming a photoresist pattern on said termination structure oxide layer to define an insulating region and to expose a region from said active region to said spacer;

etching away said exposed region using said photoresist pattern as a mask;

stripping said photoresist pattern;

removing backside unnecessary layers of said semiconductor substrate so as to expose said semiconductor substrate;

forming a second conductive material on all areas of said semiconductor substrate;

forming a photoresist pattern on said second conductive material so as to define an electrode; and

etching away exposed portion of said second conductive material so that said electrode is formed.

2. The method of claim 1, wherein said semiconductor substrate comprises a first layer and a base substrate, said first layer having a first kind of conductive impurities lightly doped and said base substrate having a first kind of conductive impurities heavily doped, still said first trenches and said second trench being formed in said first layer.

3. The method of claim 1, wherein said mesa having a width of between about 0.2-4.0 μ

m viewing along said active region to said second trench.

4. The method of claim 1, wherein said step of forming a plurality of first trenches and a second trench comprising the steps of:

forming an oxide layer on said semiconductor substrate;

forming a photoresist pattern on said oxide layer to define said plurality of first trenches and said second trench;

performing an anisotropic etching to transfer said photoresist pattern to said oxide layer;

removing said photoresist pattern;

performing an anisotropic etching to etching away said semiconductor substrate using said oxide layer as a hard mask; and

removing said oxide layer.

5. The method of claim 1, wherein said first trenches and said second trench are between about 0.4-10 μ

m in depth.

6. The method of claim 1, wherein said gate oxide layer is between about 150-3000 Å

.

7. The method of claim 1, wherein said first conductive material is a material selected from the group consisting of metal, polysilicon and amorphous silicon.

8. The method of claim 1, wherein said termination structure oxide layer is selected from the group consisting of HTO, LPTEOS, PETEOS and O₃-TEOS.

9. The method of claim 1, wherein said backside unnecessary layers comprising said gate oxide layer, said first conductive material, and said termination structure oxide layer on backside of said semiconductor substrate.

10. The method of claim 1, wherein said step of forming photoresist pattern to define an electrode is to define an anode electrode.

11. The method of claim 2, wherein said step of forming a second conductive material on all areas is to form anode on said first layer and a cathode on said backside of said semiconductor substrate.

12. The method of claim 10, wherein said anode electrode is formed to contact said active region, and said spacer, and is extended to form on a portion of said etched termination structure oxide layer so that bending region of a depletion is away from said active region at least 2.0 μ

m.

14. The method of claim 12, wherein said trench MOS devices are DMOS transistors formed in said semiconductor substrate, said semiconductor substrate comprising from top to bottom layer having a first layer, a second layer, a third layer and a base substrate, said first layer having p-type conductive impurities heavily doped, said second layer having p-type conductive impurities lightly doped, said third layer having n-type conductive impurities lightly doped, said base substrate having n-type conductive impurities heavily doped, still a plurality of n-type conductive impurities heavily doped region formed in said first layer and in an upper portion of said second layer.

15. The method of claim 12, wherein said trench MOS devices are IGBTs formed in said semiconductor substrate, said semiconductor substrate comprising from top to bottom layer having a first layer, a second layer, a third layer, a forth layer and a base substrate, said first layer having p-type conductive impurities heavily doped, said second layer having p-type conductive impurities lightly doped, said third layer having n-type conductive impurities lightly doped, said forth layer having n-type conductive impurities heavily doped, said base substrate having p-type conductive impurities heavily doped till a plurality of n-type conductive impurities heavily doped region formed in said first layer and in an upper portion of said second layer.

16. The method of claim 12, wherein said first trenches and said second trench are between about 0.4-10 μ

m in depth and are formed in said first layer, said second layer and an upper portion of said third layer.

17. The method of claim 12, wherein said mesa having a width of between about 0.4-10 μ

m, viewing along said active region to said second trench.

18. The method of claim 12, wherein said step of forming a plurality of first trenches and a second trench comprising the steps of:

forming an oxide layer on said semiconductor substrate;

forming a photoresist pattern on said oxide layer to define said plurality of first trenches and said second trench;

performing an anisotropic etching to transfer said photoresist pattern to said oxide layer;

removing said photoresist pattern;

performing an anisotropic etching to etching away said semiconductor substrate using said oxide layer as a hard mask; and

removing said oxide layer.

19. The method of claim 12, wherein said gate oxide layer is between about 150 Å

-3000 Å

.

20. The method of claim 12, wherein said first conductive material is a material selected from the group consisting of polysilicon and amorphous silicon.

21. The method of claim 12, wherein said termination structure oxide layer is selected from the group consisting of LPTEOS, PETEOS and O₃-TEOS.

22. The method of claim 12, wherein said backside unnecessary layers comprising said gate oxide layer, said first conductive material, said inter-conductive oxide layer and said termination structure oxide layer on backside of said semiconductor substrate.

24. The method of claim 14, wherein said step of forming photoresist pattern to define an electrode is to define an emitter electrode.

25. The method of claim 12, wherein said first electrode is formed to contact said active region, and said spacer, and is extended to form on a portion of said etched termination structure oxide layer so that a bending region of a depletion region away from said active region at least 2 μ

m.

13. A method of fabricating trench MOS devices and termination structure simultaneously, said method comprising the steps of:

providing a semiconductor substrate;

forming a plurality of first trenches for forming said trench MOS devices in an active region of a semiconductor substrate, and a second trench for forming said termination structure from a boundary of said active region to a margin of said semiconductor substrate, said second trench and said first trench spaced by a mesa;

performing a thermal oxidation process so as to form a gate oxide on all areas of said semiconductor substrate;

forming a first conductive layer to refill said plurality of first trenches and said second trench with a first conductive material;

performing an etching back process using a surface of said semiconductor substrate of said mesa as a stopping layer, and forming a spacer on a sidewall of said second trench;

removing said gate oxide layer using said surface of said semiconductor substrate of said mesa as a stopping layer;

performing a thermal oxidation process so as to form inter-conductive oxide layer by consuming a portion of on said semiconductor substrate and a portion of said first conductive layer;

removing said inter-conductive oxide layer using said surface of said semiconductor substrate of said mesa as a stopping layer;

forming a termination structure oxide layer on all areas of said semiconductor substrate;

forming a photoresist pattern on said termination structure oxide layer to define an insulating region and to expose a region from said active region to said spacer;

etching away said exposed region using said photoresist pattern as a mask;

stripping said photoresist pattern;

removing backside unnecessary layers of said semiconductor substrate so as to expose said semiconductor substrate;

forming a second conductive material on all areas of said semiconductor substrate so as to form a first electrode and second electrode on upper side and back side surfaces, respectively;

forming a photoresist pattern on said second conductive material so as to define a position of said first electrode; and

etching away exposed portion of said second conductive material so that said electrode is formed.

23. The method of claim 13, wherein said step of forming photoresist pattern to define a first electrode is to define a source electrode.