NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors

• US 6,310,379 B1
• Filed: 06/03/1999
• Issued: 10/30/2001
• Est. Priority Date: 06/03/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cline, Roger A., Andresen, Bernhard H.
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/325,527
• Time in Patent Office: 880 Days
• Field of Search: 257/355, 257/369, 257/362
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0277 involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor

Abstract

An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) which uses low voltage transistors (N1, N2) to provide protection to a signal pad that handles high voltage signals during normal operation of the integrated circuit. The external signal is operable at a second supply voltage that is higher than the Vdd supply voltage. The internal circuitry of the integrated circuit is comprised of MOS transistors that have gate oxide of a first thickness that has a V_ox-max suitable for the Vdd supply voltage but not for the second supply voltage. The ESD protection transistors use the same gate oxide thickness as the MOS transistors used in the internal circuitry. A substrate region in the semiconductor substrate is enclosed by a highly doped region (250) so that the back-gates of the ESD protection transistors can be voltage pumped by pump circuitry (202) in order to trigger bipolar conduction of the ESD protection transistors at a lower voltage. Control circuitry (204) is connected to the signal bond pad and to gates of the ESD protection transistors and to gates of the pump transistors to provide a voltage pulse to each gate in response to an ESD zap applied to the signal bond pad. The control circuitry provides a bias potential to the gates of the ESD protection transistors and pump transistors such that the maximum operating voltage of the gate oxide of each device is not exceeded during normal operation of the integrated circuit, thereby avoiding electrical over-stress (EOS) of the low voltage devices in the ESD protection circuitry.

Claims

1. An integrated circuit, comprising:

a semiconductor substrate connected to a reference bond pad for a reference supply voltage;

a first bus for a first supply voltage;

a first signal bond pad for connecting to an external signal, wherein the external signal is operable at approximately a second supply voltage, wherein the second supply voltage is higher than the first supply voltage;

internal circuitry connected between the first bus and semiconductor substrate comprising MOS transistors having gate oxide with a first thickness having a V_ox-max suitable for the first supply voltage but not for the second supply voltage;

ESD circuitry connected between the signal pad and the reference bond pad, wherein the ESD circuitry comprises;

a first substrate region in the semiconductor substrate enclosed by a highly doped region;

a first string of cascode connected MOS transistors each having gate oxide of the first thickness, each with a backgate in the first substrate region, a first source/drain connected to the signal pond pad, a last source/drain connected to the reference bond pad, and a separate control gate associated with each of the MOS transistors in the first string;

a second string of cascode connected MOS transistors each having a gate oxide of the first thickness, with a first source/drain connected to the signal bond pad, a last source/drain connected to the highly doped region, and a separate control gate associated with each of the MOS transistors in the second string; and

control circuitry connected to the first signal bond pad and to each of the gates in the first string and the second string operable to provide a voltage pulse to each gate in the first string and to each gate in the second string in response to an ESD zap applied to the first signal bond pad.

2. The integrated circuit of claim 1, wherein the control circuitry comprises a plurality of capacitors each having a first terminal connected to the first signal bond pad, such that each control gate of the first string of MOS transistors is connected to a second terminal of a different one of the plurality of capacitors.

3. The integrated circuit of claim 2, wherein the plurality of capacitors are connected in series and wherein the plurality of capacitors are each an MOS device having a gate oxide with the first thickness having a V_ox-max suitable for the first supply voltage but not for the second supply voltage.

4. The integrated circuit of claim 3, wherein the control circuitry further comprises a plurality of resistors connected such that respective resistors are connected to respective ones of the plurality of capacitors in a series manner.

5. The integrated circuit of claim 4, wherein a first resistor of the plurality of resistors has a terminal connected to the first bus, and a second resistor of the plurality of resistors has a terminal connected to the reference bond pad.

6. A digital system comprising:

a first integrated circuit having an output buffer operable to provide an output signal on a first terminal having fist signal voltage level;

a second integrated circuit having an output buffer with a signal bond pad connected to the first terminal, wherein the second integrated circuit further comprises;

a semiconductor substrate connected to a reference bond pad for a reference supply voltage;

a first bus for a first supply voltage, wherein the first signal voltage level is higher than the first supply voltage;

internal circuitry connected between the first bus and semiconductor substrate comprising MOS transistors having gate oxide with a first thickness having a V_ox-max suitable for the first supply voltage but not for the first signal voltage;

ESD circuitry connected between the signal pad and the reference bond pad, wherein the ESD circuitry comprises;

a first substrate region in the semiconductor substrate enclosed by a highly doped region;

a first string of cascode connected MOS transistors each having gate oxide of the first thickness, each with a backgate in the first substrate region, a first source/drain connected to the signal pond pad, a last source/drain connected to the reference bond pad, and a separate control gate associated with each of the MOS transistors in the first string;

a second string of cascode connected MOS transistors each having a gate oxide of the first thickness, with a first source/drain connected to the signal bond pad, a last source/drain connected to the highly doped region, and a separate control gate associated with each of the MOS transistors in the second string; and

control circuitry connected to the first signal bond pad and to each of the gates in the first string and the second string operable to provide a voltage pulse to each gate in the first string and to each gate in the second string in response to an ESD zap applied to the first signal bond pad.

7. The integrated circuit of claim 6, wherein the control circuitry comprises a plurality of capacitors each having a first terminal connected to the first signal bond pad, such that each control gate of the first string of MOS transistors is connected to a second terminal of a different one of the plurality of capacitors.

8. The integrated circuit of claim 7, wherein the plurality of capacitors are connected in series and wherein the plurality of capacitors are each an MOS device having a gate oxide with the first thickness having a V_ox-max suitable for the first supply voltage but not for the second supply voltage.

9. The integrated circuit of claim 8, wherein the control circuitry further comprises a plurality of resistors connected such that respective resistors are connected to respective ones of the plurality of capacitors in a series manner.

10. The integrated circuit of claim 9, wherein a first resistor of the plurality of resistors has a terminal connected to the first bus, and a second resistor of the plurality of resistors has a terminal connected to the reference bond pad.

11. A method for providing electrostatic protection for an integrated circuit, wherein the integrated circuit has internal circuitry operable at a first supply voltage and a first signal bond pad for connecting to an external signal, wherein the external signal is operable at approximately a second supply voltage and the second supply voltage is higher than the first supply voltage, and wherein the internal circuitry has MOS transistors with gate oxide having a first thickness with a V_ox-max suitable for the first supply voltage but not for the second supply voltage, comprising the steps of:

enclosing a first substrate region in a semiconductor substrate of the integrated circuit by a highly doped region;

connecting a first string of cascode connected MOS transistors having gate oxide of the first thickness between the signal bond pad and a reference bond pad, such that a backgate of each is in the first substrate region;

connecting a second string of cascode connected MOS transistors having a gate oxide of the first thickness between the signal bond pad and the highly doped region,

coupling control gates of the first string of cascode connected MOS transistors and control gates of the second string of cascode connected MOS transistors to the signal bond pad;

pumping the first substrate region in response to an ESD zap applied to the first signal bond pad by turning on the second string of cascode connected MOS transistors via the coupled control gates; and

turning on the first string of cascode connected MOS transistors in response to the ESD zap via the coupled control gates before the second string of cascode connected transistors and the internal circuitry is damaged by the ESD zap.

12. The method of claim 11, further comprising the step of overriding the step of coupling during normal operation when the second supply voltage is provided to the integrated circuit.