Electric circuit and package for semiconductor

• US 6,310,393 B1
• Filed: 10/05/1999
• Issued: 10/30/2001
• Est. Priority Date: 10/09/1998
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Iwaki, Hideki, Fukumoto, Yukihiro, Taguchi, Yutaka, Ogura, Tetsuyosi, Bessho, Yoshihiro
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): CRUZ, LOURDES C
• Application Number:
  US09/412,593
• Time in Patent Office: 756 Days
• Field of Search: 257/531, 257/532, 257/723, 257/724, 438/107, 438/110
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

The semiconductor package of this invention includes: a semiconductor element having a power supply terminal, a ground terminal, and an output terminal; an inductance; and a capacitance. One of opposing terminals of the capacitance is connected to the power supply terminal of the semiconductor element, and the other terminal is connected to the ground terminal of the semiconductor element. The ground terminal of the semiconductor element is connected to a ground terminal of the semiconductor package, the power supply terminal of the semiconductor element is connected to a power supply terminal of the semiconductor package via the inductance, and the output terminal of the semiconductor element is connected to an output terminal of the semiconductor package.

Claims

1. An electric circuit comprising:

a semiconductor element having at least one power supply terminal and at least one ground terminal;

at least one non-parasitic inductance; and

at least one capacitance,

wherein one terminal of opposing terminals of the capacitance is connected to the power supply terminal and the other terminal is connected to the ground terminal,

the power supply terminal is connected to a power supply, and

the ground terminal is grounded exclusively via the inductance.

2. A semiconductor package comprising:

(1) a semiconductor element having at least one power supply terminal, at least one ground terminal, and at least one output terminal;

(2) at least one non-parasitic inductance; and

(3) at least one capacitance,

wherein one terminal of opposing terminals of the capacitance is connected to the power supply terminal of the semiconductor element and the other terminal is connected to the ground terminal of the semiconductor element,

the ground terminal of the semiconductor element is connected to a ground terminal of the semiconductor package without a capacitive element therebetween,

the power supply terminal of the semiconductor element is connected to a power supply terminal of the semiconductor package via the inductance, and

the output terminal of the semiconductor element is connected to an output terminal of the semiconductor package.

7. A semiconductor package according to claim 2, further comprising:

a substrate on which the semiconductor package is mounted, the substrate having a ground plane formed on an inner layer,

wherein a signal line is connected to the output terminal of the semiconductor element, and

the ground plane is formed on a first inner layer under the signal line.

12. A semiconductor package according to any of claims 2 to 5, wherein the capacitance is a chip capacitor.

13. A semiconductor package according to any of claims 2 to 5, wherein the capacitance is a thick film capacitor formed on an inner layer or surface layer of a substrate of the semiconductor package.

14. A semiconductor package according to any of claims 2 to 5, wherein the inductance is an inductor formed of an interconnect of the semiconductor package.

15. A semiconductor package according to any of claims 2 to 5, wherein the inductance is a chip inductor.

16. A semiconductor package according to any of claims 2 to 5, further comprising a carrier substrate on which the semiconductor element, the capacitance, and the inductance are to be mounted,

wherein the carrier substrate is a ceramic substrate or a resin multi-layer substrate.

17. A semiconductor package according to any of claims 2 to 5, wherein at least one terminal selected from the power supply terminal and the ground terminal of the semiconductor package is adjacent to the output terminal or the differential output terminals.

18. A semiconductor package according to any of claims 2 to 5, wherein the capacitance is a thin film capacitor formed on an inner layer or surface layer of a substrate of the semiconductor package.

3. A semiconductor package comprising:

(1) a semiconductor element having at least one power supply terminal, at least one ground terminal, and at least one output terminal;

(2) at least one non-parasitic inductance; and

(3) at least one capacitance,

wherein one terminal of opposing terminals of the capacitance is connected to the power supply terminal of the semiconductor element and the other terminal is connected to the ground terminal of the semiconductor element,

the power supply terminal of the semiconductor element is connected to a power supply terminal of the semiconductor package,

the ground terminal of the semiconductor element exclusively is connected to a ground terminal of the semiconductor package via the inductance, and

the output terminal of the semiconductor element is connected to an output terminal of the semiconductor package.

8. A semiconductor package according to claim 3, further comprising:

a substrate on which the semiconductor package is mounted, the substrate having a power supply plane formed on an inner layer,

wherein a signal line is connected to the output terminal of the semiconductor element, and

the power supply plane is formed on a first inner layer under the signal line.

4. A semiconductor package comprising:

(1) a semiconductor element having at least one power supply terminal, at least one ground terminal, and at least one output terminal;

(2) at least two inductances; and

(3) at least one capacitance,

wherein one terminal of opposing terminals of the capacitance is connected to the power supply terminal of the semiconductor element and the other terminal is connected to the ground terminal of the semiconductor element,

the ground terminal of the semiconductor element is connected to a first ground terminal of the semiconductor package,

the power supply terminal of the semiconductor element is connected to a first power supply terminal of the semiconductor package,

the ground terminal of the semiconductor element is connected to a second ground terminal of the semiconductor package via a first inductance of the at least two inductances,

the power supply terminal of the semiconductor element is connected to a second power supply terminal of the semiconductor package via a second inductance of the at least two inductances, and

the output terminal of the semiconductor element is connected to an output terminal of the semiconductor package.

9. A semiconductor package according to claim 4, further comprising:

a substrate on which the semiconductor package is mounted, the substrate having a ground plane and a power supply plane formed on respective inner layers,

wherein a signal line is connected to the output terminal of the semiconductor element,

the ground plane is formed on a first inner layer of the inner layers under the signal line,

the first ground terminal is connected to the ground plane, and

the second power supply terminal is connected to the power supply plane.

10. A semiconductor package according to claim 4, further comprising:

a substrate on which the semiconductor package is mounted, the substrate having a ground plane and a power supply plane formed on respective inner layers,

wherein a signal line is connected to the output terminal of the semiconductor element,

the power supply plane is formed on a first inner layer of the inner layers under the signal line,

the first power supply terminal is connected to the power supply plane, and

the second ground terminal is connected to the ground plane.

5. A semiconductor package comprising:

(1) a semiconductor element having at least one power supply terminal, at least one ground terminal, and at least one pair of differential output terminals;

(2) at least two inductances; and

(3) at least one capacitance,

wherein one terminal of opposing terminals of the capacitance is connected to the power supply terminal of the semiconductor element and the other terminal is connected to the ground terminal of the semiconductor element,

the ground terminal of the semiconductor element is connected to a ground terminal of the semiconductor package via the first inductance of the at least two inductances,

the power supply terminal of the semiconductor element is connected to a power supply terminal of the semiconductor package via the second inductance of the at least two inductances, and

the pair of differential output terminals of the semiconductor element are connected to a pair of differential output terminals of the semiconductor package.

11. A semiconductor package according to claim 5, further comprising:

a substrate on which the semiconductor package is mounted, the substrate having a power supply, a ground terminal, and differential signal terminals,

wherein the power supply terminal of the semiconductor package is connected to the power supply of the substrate,

the ground terminal of the semiconductor package is connected to the ground terminal of the substrate, and

the pair of differential output terminals of the semiconductor package are connected to the differential signal terminals.

6. An electric circuit comprising:

(1) a semiconductor element having at least one power supply terminal, at least one ground terminal, and at least one pair of differential output terminals;

at least two inductances; and

at least one capacitance,

wherein one terminal of opposing terminals of the capacitance is connected to the power supply terminal of the semiconductor element and the other terminal is connected to the ground terminal of the semiconductor element,

the ground terminal of the semiconductor element is grounded via a first inductance of the at least two inductances,

the power supply terminal of the semiconductor element is connected to a power supply via a second inductance of the at least two inductances, and

the pair of differential output terminals of the semiconductor element are connected to a pair of terminals.