Latch circuit for latching data at an edge of a clock signal

• US 6,310,501 B1
• Filed: 11/24/1999
• Issued: 10/30/2001
• Est. Priority Date: 11/27/1998
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: NEC Corporation
• Inventors: Yamashita, Kazuo
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US09/449,234
• Time in Patent Office: 706 Days
• Field of Search: 327/208, 327/210-212, 327/215, 327/219, 327/55
• US Class Current: 327/215
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

A latch circuit comprises a delaying inverter circuit 1 for inverting a clock signal CLK with a predetermined delay, a precharge circuit for precharging a first node A and a second node B of the latch circuit to a predetermined potential during a time period in which the clock signal is in a first logic level, a first amplifier circuit for providing a potential difference between the first node A and the second node B in response to an input signal DIN during a first time period in which the clock signal CLK and an output signal iCLK of the delaying inverter circuit are in a second logic level, a second amplifier circuit for amplifying the potential difference between the first node and the second node during a time period in which the clock signal is in the second logic level and a flip-flop circuit adapted to be set and reset according to the potentials at the first and second nodes.

Claims

1. A latch circuit comprising:

a delaying inverter circuit for inverting a clock signal with a predetermined delay;

a precharging circuit for precharging first and second nodes of said latch circuit to a predetermined potential during a time period in which the clock signal is at a first logic level;

a first amplifier circuit for providing a potential difference between said first and second nodes in response to an input signal during a first time period in which the clock signal and an output signal of said delaying inverter circuit are at a second logic level, wherein said first amplifier means comprises a first transistor group and a second transistor group for pulling out one of charges of said first and second nodes during the first time period;

second amplifier circuit for amplifying the potential difference between said first node and said second node during a second time period; and

a flip-flop circuit adapted to be set and reset according to the potentials at the first and second nodes,

wherein said first amplifier circuit comprises;

a first transistor group including a first transistor having a gate supplied with the input signal, a second transistor having a gate supplied with the clock signal and a third transistor having a gate supplied with an output of said delaying inverter circuit, said first, second and third transistors being connected in series between said first node and a power source; and

a second transistor group including a fourth transistor having a gate supplied with an inverted signal of the input signal, a fifth transistor having a gate supplied with the clock signal and a sixth transistor having a gate supplied with the output signal of said delaying inverter circuit, said fourth, fifth and sixth transistors being connected in series between said second node and said power source.

2. A latch circuit as claimed in claim 1, wherein said second amplifier circuit comprises:

a first inverter circuit having an input terminal connected to said second node and an output terminal connected to said first node;

a second inverter circuit having an input terminal connected to said first node and an output terminal connected to said second node; and

a power supply circuit for supplying a power supply voltage during a time period in which the clock signal is at the second logic level.