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Reference-free clock generation and data recovery PLL

  • US 6,310,521 B1
  • Filed: 12/23/1999
  • Issued: 10/30/2001
  • Est. Priority Date: 12/23/1999
  • Status: Expired due to Term
First Claim
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1. An apparatus comprising:

  • a first circuit configured to generate one or more first control signals having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said first data rate;

    a second circuit configured to generate one or more second control signals having said first data rate in response to (i) said input signal and (ii) said clock signal; and

    a first logic circuit configured to generate said clock signal in response to (i) said one or more first control signals, (ii) said one or more second control signals and (iii) a third control signal, wherein one of said first control signals and said second control signals comprises a pump-up signal and another one of said first control signals and said second control signals comprises a pump-down signal.

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