Reference-free clock generation and data recovery PLL

• US 6,310,521 B1
• Filed: 12/23/1999
• Issued: 10/30/2001
• Est. Priority Date: 12/23/1999
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Dalmia, Kamal
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US09/471,576
• Time in Patent Office: 677 Days
• Field of Search: 331/1.A, 331/10, 331/11, 331/14, 331/17, 331/18, 331/25, 331/DIG.2, 327/156-159, 455/260, 375/376
• US Class Current: 331/11
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

An apparatus comprising a first circuit, a second circuit, and a logic circuit. The first circuit may be configured to generate one or more first control signals having a first data rate in response to an input signal having a second data rate and a clock signal having the first data rate. The second circuit may be configured to generate one or more second control signals in response to the input signal and the clock signal. The first logic circuit may be configured to generate the clock signal in response to the one or more first control signals, the one or more second control signals and a third control signal.

Claims

1. An apparatus comprising:

a first circuit configured to generate one or more first control signals having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said first data rate;

a second circuit configured to generate one or more second control signals having said first data rate in response to (i) said input signal and (ii) said clock signal; and

a first logic circuit configured to generate said clock signal in response to (i) said one or more first control signals, (ii) said one or more second control signals and (iii) a third control signal, wherein one of said first control signals and said second control signals comprises a pump-up signal and another one of said first control signals and said second control signals comprises a pump-down signal.

2. The apparatus according to claim 1 further comprising:

a second logic circuit configured to generate said third control signal in response to (i) said one or more second control signals and (ii) said clock signal.

3. The apparatus according to claim 1, wherein said first circuit is further configured to generate an output signal having a second data rate.

4. The apparatus according to claim 1, wherein said first circuit comprises a digital linear phase detector and said second circuit comprises a digital frequency detector.

5. The apparatus according to claim 3, wherein said output signal comprises a re-timed data signal and said clock signal comprises a recovered clock signal.

6. The apparatus according to claim 2, wherein said second logic circuit comprises a gate and a counter, wherein said counter is configured to generate said third control signal.

7. The apparatus according to claim 6, wherein said counter is configured to (i) calculate a count signal and (ii) reset said count signal in response to said gate and said logic signal.

8. The apparatus according to claim 7, wherein said gate is configured to control said counter in response to said one or more second control signals.

9. The apparatus according to claim 8, wherein said first logic circuit is further configured to select either (i) said one or more first control signals or (ii) said one or more second control signals.

10. The apparatus according to claim 1, further comprising a third logic circuit configured to control said second logic circuit in response to (i) said first logic circuit, (ii) said control signal and (iii) said logic signal.

11. The apparatus according to claim 10, wherein said apparatus comprises a reference-less single active loop clock and data recovery PLL architecture.

12. The apparatus according to claim 1, wherein said first logic circuit comprises:

a multiplexer configured to receive said first and second control signals and present one or more selected control signals in response to said third control signal;

a charge pump filter configured to present a filter control signal in response to said selected control signals; and

a voltage controlled oscillator configured to generate said clock signal in response to said filter control signal.

13. An apparatus comprising:

means for generating one or more first control signals having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said first data rate;

means for generating one or more second control signals having said first data rate in response to (i) said input signal and (ii) said clock signal; and

means for generating said clock signal in response to (i) said one or more first control signals, (ii) said one or more second control signals and (iii) a third control signal, wherein one of said first control signals and said second control signals comprises a pump-up signal and another one of said first control signals and said second control signals comprises a pump-down signal.

14. A method for reference-free clock generation and data recovery, comprising the steps of:

(A) generating one or more first control signals having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said first data rate;

(B) generating one or more second control signals having said first data rate in response to (i) said input signal and (ii) said clock signal; and

(C) generating said clock signal in response to (i) said one or more first control signals, (ii) said one or more second control signals and (iii) a third control signal, wherein one of said first control signals and said second control signals comprises a pump-up signal and another one of said first control signals and said second control signals comprises a pump-down signal.

15. The method according to claim 14, further comprising the step of:

(D) generating said third control signal in response to said one or more second signals and said logic signal.

16. The method according to claim 14, wherein said output signal comprises a re-timed data signal and said clock signal comprises a recovered clock signal.

17. The method according to claim 15, wherein step (D) further comprises (i) calculating a count and (ii) resetting said count in response to said gate and said logic signal.

18. The method according to claim 14, wherein step (C) further comprises selecting either said one or more first control signals or said one or more second control signals.

19. The method according to claim 15, further comprising the step of:

(E) controlling said step (D) in response to (i) said third control signal and (ii) said clock signal.