Manufacturing method of liquid crystal display preventing RF discharge damage

• US 6,310,666 B1
• Filed: 03/12/1998
• Issued: 10/30/2001
• Est. Priority Date: 10/24/1997
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Moon, Kyo Ho
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): Nguyen, Francis
• Application Number:
  US09/038,823
• Time in Patent Office: 1,328 Days
• Field of Search: 438/149, 438/151, 438/59, 257/62, 257/59, 257/291, 349/40-43, 349/139, 349/54, 349/46, 349/147, 349/122, 345/87, 345/205-206, 345/92, 445/24-25
• US Class Current: 349/40
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures

Abstract

A method for manufacturing a liquid crystal display device, includes the steps of forming a gate line, a gate pad at an end of the gate line, and a gate shorting bar connected to the gate pad on a substrate, wherein the gate shorting bar is offset from an edge of the substrate, and depositing a gate insulation layer completely covering the gate line, the gate pad, and the gate shorting bar.

Claims

1. A method for manufacturing a liquid crystal display device, comprising the step of:

forming a gate electrode and a gate line on a substrate;

forming a gate pad at an end of the gate line;

forming a gate shorting bar connected to the gate pad; and

depositing a gate insulation layer on the gate electrode, the gate line, the gate pad, and the gate shorting bar,

wherein the gate shorting bar is formed a distance away from an edge of the substrate so that the gate insulation layer completely covers all portions of the gate line, the gate pad, and the gate shorting bar, which are above the substrate.

2. The method of claim 1, further including the steps of:

forming a semiconductor layer over the gate insulation layer and over the gate electrode;

forming a doped semiconductor layer on the semiconductor layer;

forming a source electrode on the doped semiconductor, a data line extending from the source electrode, a data pad at an end of the data line, a data shorting bar connected to the data pad, and a drain electrode facing the source electrode connected to the doped semiconductor layer;

forming a protection layer covering the data line, the data pad, the data shorting bar, the source electrode, and the drain electrode;

forming a contact hole in the protection layer exposing a portion of the drain electrode; and

forming a pixel electrode connected to the drain electrode through the contact hole,

wherein the protection layer completely covers the data line, the data pad, the data shorting bar, the source electrode, and the drain electrode.

3. The method of claim 2, wherein outer edges of the gate shorting bar and the data shorting bar are formed a distance away from the edge of the substrate.

4. The method of claim 1, wherein the step of depositing a gate insulation layer includes forming a layer selected from the group consisting of silicon nitride and silicon oxide.

5. The method of claim 2, wherein the step of forming a protection layer includes forming a layer selected from the group consisting of silicon nitride, silicon oxide, and benzo-cyclo-butene.

6. The method of claim 2, wherein the step of forming a contact hole includes a step of etching the protection layer with an etchant gas selected from the group consisting of SF₆ and CF₄ and converted to a plasma state by use of a radio frequency generator.

7. A method for manufacturing a liquid crystal display device, comprising the steps of:

forming a gate electrode, a gate line, a gate pad at an end of the gate line, a gate shorting bar connected to the gate pad, a data pad, and a data shorting bar connected to the data pad on a substrate; and

depositing a gate insulation layer,

wherein the gate shorting bar and the data shorting bar are formed a distance away from an edge of the substrate, and the gate insulation layer completely covers all portions of the gate line, the gate pad, the gate shorting bar, the data pad, and the data shorting bar, which are above the substrate.

8. The method of claim 7, further including the steps of:

forming a semiconductor layer on the gate insulation layer over the gate electrode;

forming a doped semiconductor layer on the semiconductor layer;

etching the gate insulation layer to form a data contact hole exposing a portion of the data pad;

forming a data line connected to the data pad through the data contact hole, a source electrode extending from the data line and in contact with the doped semiconductor layer, and a drain electrode facing the source electrode and in contact with the doped semiconductor layer;

forming a protection layer completely covering the source electrode, the drain electrode, the data line, the data pad, the data shorting bar, the gate electrode, the gate line, the gate pad, and the gate shorting bar;

forming a contact hole in the protection layer exposing a portion of the drain electrode; and

forming a pixel electrode connected to the drain electrode through the contact hole.

9. The method of claim 8, wherein the step of forming a contact hole includes a step of etching the protection layer with an etchant gas selected from the group consisting of SF₆ and CF₄ and converted to a plasma state by use of a radio frequency generator.

10. The method of claim 8, wherein the step of forming a protection layer includes forming a layer selected from the group consisting of silicon nitride, silicon oxide, and benzo-cyclo-butene.

11. The method of claim 7, wherein the step of depositing a gate insulation layer includes forming a layer selected from the group consisting of silicon nitride or silicon oxide.

12. The method of claim 7, wherein the step of forming a gate line, a gate pad at the end of the gate line, a gate shorting bar connected to the gate pad, a data pad, and a data shorting bar connected to the data pad on the substrate further includes forming the gate shorting bar and the data shorting bar distance away from the edge of the substrate.

13. A method of forming a liquid crystal display device, comprising the steps of:

forming a gate electrode, a gate line connected to the gate electrode, a gate pad connected to the gate line, and a gate shorting bar connected to the gate pad on a substrate, wherein the gate shorting bar is formed a distance away from an edge of the substrate;

forming a gate insulation layer completely covering all portions of the gate electrode, the gate line, the gate pad, the gate shorting bar, and an area of the substrate between the gate shorting bar and the edge of the substrate, which are above the substrate;

forming a semiconductor layer over the gate insulation layer and over the gate electrode;

forming a source electrode and a drain electrode over the semiconductor layer, wherein the drain electrode faces the source electrode; and

forming a protection layer over the gate insulation layer, the source electrode and the drain electrode.

14. The method of claim 13, further including the step of forming a pixel electrode over the protection layer and in contact with the drain electrode.

15. The method of claim 14, wherein the step of forming a pixel electrode over the protection layer and in contact with the drain electrode includes forming a contact hole in the protection layer over the drain electrode.

16. The method of claim 13, further including the step of forming a data line connected to the source electrode, a data pad connected to the data line, and a data shorting bar connected to the data pad, wherein the data shorting bar is formed a distance away from an edge of the substrate.

17. The method of claim 16, wherein the protection layer completely covers the date line, the data pad, the data shorting bar, and an area between the data shorting bar and the edge of the substrate.

18. The method of claim 13, wherein the step of forming a semiconductor layer over the gate insulation layer and over the gate electrode includes forming an undoped semiconductor layer and a doped semiconductor layer over the undoped semiconductor layer.