Semiconductor integrated circuit device including tester circuit for defective memory cell replacement

• US 6,310,807 B1
• Filed: 03/22/2001
• Issued: 10/30/2001
• Est. Priority Date: 10/06/2000
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hidaka, Hideto, Ooishi, Tsukasa
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/813,917
• Time in Patent Office: 222 Days
• Field of Search: 365/201, 365/207, 365/208, 365/210, 365/241
• US Class Current: 365/200
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. A row decoder selects a plurality of memory cells belonging to the same row in the memory cell array at one time according to an address signal. A BIST circuit determines that repair is to be carried out with a spare memory cell row, not a spare memory cell column, when a plurality of defective memory cells are detected from the plurality of memory cells selected at one time.

Claims

1. A semiconductor integrated circuit device comprising:

a memory cell array having a plurality of memory cells arranged in a matrix, each memory cell storing data,

said memory cell array including

a normal memory cell array with a plurality of normal memory cells,

a spare memory cell row with a plurality of spare memory cell rows, and

a spare memory cell column with a plurality of spare memory cell columns;

a memory cell select circuit to select a plurality of memory cells belonging to the same row in said memory cell array at one time according to an address signal;

a data transmission circuit to transfer said stored data with respect to said selected plurality of memory cells; and

tester circuit detecting a defective memory cell in said memory cells, and determining which of said spare memory cell is to be used for replacement,

said tester circuit including

a comparison circuit comparing stored data from said selected memory cell with expected value data in a test readout operation,

an address storage circuit to store a defective address corresponding to a defective memory cell according to a comparison result of said comparison circuit, and

a control circuit to control a test operation, said control circuit determining repair using said spare memory cell row when a plurality of defective memory cells are detected from said plurality of memory cells selected at one time.

2. The semiconductor integrated circuit device according to claim 1, wherein said tester circuit further includes a signal generation circuit generating said address signal to sequentially select said memory cell, test data to be written into said memory cell selected in a test write operation, and said expected value data to be read out from said memory cell in a test read operation.

3. The semiconductor integrated circuit device according to claim 1, wherein said control circuit determines repair using said spare memory cell row when more defective memory cells than the number of said spare memory cell columns are detected from said plurality of memory cells selected at one time.

4. The semiconductor integrated circuit device according to claim 1, wherein said memory cell select circuit selects n×

n (n;

natural number) memory cells at one time,

wherein said comparison circuit includes

a match detection circuit comparing data read out from said n×

n memory cells selected with the expected value, and generating n×

n match detection signals indicating a matching result,

n first logic gates provided for each column of a signal matrix formed of said n×

n match detection signals to determine whether n corresponding match detection signals match,

n second logic gates provided for each row of the signal matrix formed of said n×

n match detection signals to determine whether n corresponding match detection signals match, and

a third logic gate receiving outputs of said first and second logic gates to determine whether there is a signal indicating mismatch out of said n×

n match detection signals.

5. The semiconductor integrated circuit device according to claim 4, wherein said comparison circuit further includes

n first parity determination circuits provided for each column of the signal matrix formed of said n×

n match detection signals to determine parity of corresponding n match detection signals,

n second parity determination circuits provided for each row of the signal matrix formed of said n×

n match detection signals to determine parity of corresponding n match detection signals,

a plurality of first defective detection circuits provided for each column of said signal matrix to detect the number of match detection signals indicating mismatch included in a column of said signal matrix according to a determination result of a corresponding said first parity determination circuit and a determination result of a corresponding said first logic gate,

a first defective number add circuit to add the detected result of said plurality of first defective detection circuits,

a plurality of second defective detection circuits provided for each row in said signal matrix to detect the number of match detection signals indicating mismatch included in a row of said signal matrix according to a determination result of a corresponding said second parity determination circuit and a corresponding said second logic gate,

a second defective number add circuit to add the detected result of said plurality of second defective detection circuits, and

defective number determination circuit receiving outputs of said first and second defective add circuits to provide the output of the larger number of addition as the defective number.

6. The semiconductor integrated circuit device according to claim 1, said memory cell select circuit further including means for selecting individually said spare memory cell row and spare memory cell column according to said address signal.

7. The semiconductor integrated circuit device according to claim 6, wherein said address signal comprises

a plurality of bits of normal address signals to select a memory cell in said normal memory cell array, and

an additional bit to select individually said spare memory cell row and spare memory cell column.

8. The semiconductor integrated circuit device according to claim 7, said address storage circuit further including means for storing identification information to identify that a detected defective address corresponds to said spare memory cell row and spare memory cell column.

9. The semiconductor integrated circuit device according to claim 8, said memory cell select circuit including a defective address storage circuit to store a detected defective address, and when said address signal matches said defective address, suppress selection of a normal memory cell and select any of said spare memory cell row and spare memory cell column.

10. The semiconductor integrated circuit device according to claim 9, wherein said memory cell select circuit carries out replacement with any of said spare memory cell row and spare memory cell column that is not defective according to said identification information.