Design of microelectronic process flows for manufacturability and performance

• US 6,311,096 B1
• Filed: 04/01/1999
• Issued: 10/30/2001
• Est. Priority Date: 04/01/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Saxena, Sharad, Mozumder, Purnendu K., Davis, Joseph C., Vasanth, Karthik, Burch, Richard G., Rao, Suraj
• Primary Examiner(s): Grant, William
• Assistant Examiner(s): CABRERA, ZOILA E
• Application Number:
  US09/283,479
• Time in Patent Office: 943 Days
• Field of Search: 700/93, 700/102, 700/108, 700/109, 700/110, 700/121, 438/14
• US Class Current: 700/121
• CPC Class Codes: G06Q 10/06 Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling

Abstract

A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the sequential and stochastic nature of semiconductor manufacturing and enables the separation of device and process models, statistical modeling of process modules from observable wafer states and approximations for statistical optimization over large design spaces. The statistical estimation component of this method results in extremely accurate predictions of the variability of transistor performance for all of the fabricated flows. Statistical optimization results in devices that achieve all transistor performance and reliability goals and reduces the variability of key transistor performances.

Claims

1. A method of improving process flow in fabrication process for fabrication of a device which comprises the steps of:

(a) providing a model of the process flow as a sequence of process modules which is a sequence of contiguous process steps for providing a device falling within a predetermined window;

(b) for a first said process module, determining the probability of the state of the device being fabricated being in any one of plural states as a result of a first fabrication process for maximizing the probability of said device being within said window;

(c) for a second said process model, determining the probablitily of the state of the device being fabricated being in any one of plural states as a result of a second fabrication process and the result of said first fabrication process for maximizing the probability of said device being within said window; and

(d) altering at least one of said first and second processes in response to results of fabrication of said device to further maximixe the probability that the device performance falls within said window.

2. The method of claim 1 wherein the effect of process variations introduced into each said process module is represented by a Markov chain.

3. The method of claim 1 wherein wherein each said process module transforms the state of the incoming device.

4. The method of claim 1 wherein, the state of a device is represented as a vector of the structure and parameters that affect device performance and/or reliability.

5. The method of claim 2 wherein, the state of a device is represented as a vector of the structure and parameters that affect device performance and/or reliability.

6. The method of claim 3 wherein, the state of a device is represented as a vector of the structure and parameters that affect device performance and/or reliability.

7. The method of claim 1 wherein said process flow is a semiconductor fabrication process flow.

8. The method of claim 2 wherein said process flow is a semiconductor fabrication process flow.

9. The method of claim 3 wherein said process flow is a semiconductor fabrication process flow.

10. The method of claim 4 wherein said process flow is a semiconductor fabrication process flow.

11. The method of claim 5 wherein said process flow is a semiconductor fabrication process flow.

12. The method of claim 6 wherein said process flow is a semiconductor fabrication process flow.