UART support for address bit on seven bit frames

• US 6,311,235 B1
• Filed: 10/31/1998
• Issued: 10/30/2001
• Est. Priority Date: 10/31/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Typaldos, Melanie D.
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US09/184,277
• Time in Patent Office: 1,095 Days
• Field of Search: 228/180.22, 710/1-4, 710/8-12, 710/22-30, 710/33-35, 710/58-64, 710/65, 702/114, 370/510, 370/359, 370/439, 340/505, 340/825.44, 340/825.52, 340/825.65, 358/1.12, 358/1.13, 358/1.14
• US Class Current: 710/33
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

An asynchronous serial port provides increased serial throughput. In data frames comprising eight data bits, at least one bit may be disabled. The status and communication bits within the frame are moved into the locations of the disabled bits. The number of bits in the transmission data frame is thus reduced by the number of disabled data bits.

Claims

1. A microcontroller comprising:

an execution unit for executing instructions; and

an asynchronous serial port for communicating asynchronous frames having a frame length, each frame comprising at least one data bit and an address bit, wherein the asynchronous serial port is selectably configurable by the execution unit to communicate either n or n−

1 data bits, for n greater than 1, prior to an address bit, the placement of the address bit being independent of frame length.

2. The microcontroller of claim 1, wherein n is equal to eight data bits.

3. The microcontroller of claim 1, wherein the asynchronous frame further contains a parity bit.

4. The microcontroller of claim 3, wherein the parity bit occurs after the address bit.

5. The microcontroller of claim 1, further having a transmitting mode wherein the data frames are transmitted according to the data bit configuration.

6. The microcontroller of claim 1, further having a receiving mode wherein data frames are received according to the data bit configuration.

7. The receiving mode of claim 6, wherein when the address bit of a received data frame is asserted, address matching is enabled.

8. The receiving mode of claim 6, wherein when the address bit of a received data frame is asserted, an interrupt is created to the execution unit.

9. The microcontroller of claim 1, wherein the transmission and reception of n or n−

1 data bits is controlled by a seven data bit enable bit in a control register.

10. The microcontroller of claim 1, wherein the transmission and reception of address bits is controlled by a address bit enable bit in a control register.

11. The microcontroller of claim 1, wherein the data for transmission and the address bit for transmission comes from a data register.

12. The microcontroller of claim 1, wherein the data for transmission comes from a data register and the address bit for transmission comes from a register other than the data register.

13. The microcontroller of claim 12, wherein the address bit for transmission comes from a control register.

14. An asynchronous serial port for communicating asynchronous frames having a frame length, each frame comprising at least one data bit and an address bit, wherein the asynchronous serial port is selectably configurable by the execution unit to communicate either n or n−

1 data bits, for n greater than 1, prior to an address bit the placement of the address bit being independent of frame length.

15. The asynchronous serial port of claim 14, wherein n is equal to eight data bits.

16. The asynchronous serial port of claim 14, wherein the asynchronous frame further contains a parity bit.

17. The asynchronous serial port of claim 16, wherein the parity bit occurs after the address bit.

18. The asynchronous serial port of claim 14, further having a transmitting mode wherein the data frames are transmitted according to the data bit configuration.

19. The asynchronous serial port of claim 14, further having a receiving mode wherein data frames are received according to the data bit configuration.

20. The receiving mode of claim 19, wherein when the address bit of a received data frame is asserted, address matching is enabled.

21. The receiving mode of claim 19, wherein when the address bit of a received data frame is asserted, an interrupt is created to the execution unit.

22. The asynchronous serial port of claim 14, wherein the transmission and reception of n or n−

1 data bits is controlled by a seven data bit enable bit in a control register.

23. The asynchronous serial port of claim 14, wherein the transmission and reception of address bits is controlled by a address bit enable bit in a control register.

24. The asynchronous serial port of claim 14, wherein the data for transmission comes from a data register and the address bit for transmission comes from a register other than the data register.

25. The asynchronous serial port of claim 24, wherein the address bit for transmission comes from a control register.