Data buffer apparatus and method for storing graphical data using data encoders and decoders

• US 6,311,258 B1
• Filed: 02/18/1998
• Issued: 10/30/2001
• Est. Priority Date: 04/30/1997
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Chung, Wing Yan, Gibson, Ian
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US09/025,843
• Time in Patent Office: 1,350 Days
• Field of Search: 710/208, 710/209, 710/211, 710/212, 711/208-220, 711/150, 711/200, 358/427, 341/50, 341/65, 382/246, 382/166, 382/232, 382/244
• US Class Current: 711/200
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering

Abstract

A data buffer apparatus stores first data objects containing a plurality of first data items and second data objects containing one or more second data items in a number of different ways depending upon a mode of operation. The apparatus includes an encoder (1290) for rearranging the order of the first data items within the first data objects in accordance with first arranging mode, prior to storing in the buffer (1293). The apparatus also includes a decoder (1291) for rearranging the order of a plurality first data items read from the buffer, in accordance with a second arranging mode.

Claims

1. A data store apparatus adapted to store first data objects comprised of a plurality of first data items and to store second data objects comprised of one or more second data items, said data store apparatus comprising:

an encoder unit adapted to receive the first data objects and the second data objects during a first operating mode and a second operating mode, respectively, of said data store apparatus, to encode the first data objects by rearranging an order of the plurality of first data items of the first data objects during the first operating mode of said data store apparatus, and to encode the second data objects by not rearranging an order of the one or more second data items of the second data objects during the second operating mode of said data store apparatus;

a storage unit adapted to store the encoded first data objects and the encoded second data objects during the first operating mode and the second operating mode, respectively;

a decoder unit adapted to rearrange an order of an output of said storage unit during the first operating mode, and not to rearrange an order of an output of said storage unit during the second operating mode of said data store apparatus;

an address generator unit adapted to generate read and write addresses for said storage unit in accordance with the first operating mode and the second operating mode; and

a controller unit adapted to generate control signals dependent upon the first operating mode and the second operating mode for controlling an order of data items encoded by said encoder unit, storage of the encoded first data objects or the encoded second data objects in said storage unit, an output operation of said decoder unit, and generation of the read and write addresses by said address generator unit.

2. A data store apparatus as claimed in claim 1, wherein said encoder unit comprises a plurality of logic circuits, such as multiplexers, adapted to rearrange the plurality of first data items of the first data objects into a required internal data format as determined by said controller unit.

3. A data store apparatus as claimed in claim 1, wherein said storage unit comprises:

a plurality of memory modules adapted to store encoded data objects; and

a read address multiplexer adapted to multiplex the read addresses to produce internal read addresses for the plurality of memory modules that comprise said storage unit.

4. A data store apparatus as claimed in claim 1, wherein said decoder unit comprises a plurality of logic circuits adapted to rearrange the output of said storage unit during the first operating mode into a required output data format.

5. A data store apparatus as claimed in claim 1, wherein said address generator unit comprises a plurality of logic circuits adapted to calculate memory write addresses and memory read addresses for said storage unit.

6. A data store apparatus as claimed in claim 1, wherein said controller unit comprises a plurality of logic circuits adapted to generate the control signals.

7. A data store apparatus as claimed in claim 1, wherein

the first operating mode is a JPEG compression mode, the first data objects are pixel data, and the plurality of first data items are single color component data of the pixel data, and

said data store apparatus is utilized for storing the pixel data and retrieving the single color component data for minimum coded unit decomposition during a JPEG compression operation.

8. A data store apparatus as claimed in claim 1, wherein

the first operating mode is a JPEG compression mode, the first data objects are each single color component block data, and the plurality of first data items are single color component data of the block data, and

said data store apparatus is utilized for storing the single color component block data and retrieving pixel data for minimum coded unit reconstruction during a JPEG decompression operation.

9. A data store apparatus as claimed in claim 1, wherein

the second operating mode is a color space conversion mode,

the second data objects comprise interval values of an interval table and fractional values of a fractional table, and

said data store apparatus is utilized for storing and retrieving the second data objects for a color space conversion operation.

10. A data store apparatus as claimed in claim 1, wherein

the second operating mode is a convolution and image transformation mode,

the second data objects comprise coefficients of a matrix, and

said data apparatus is utilized for storing and retrieving matrix coefficients as second data objects for operations that involve matrix multiplication.

11. A data store apparatus as claimed in claim 1,

wherein said storage unit comprises a plurality of separately addressable memory banks each utilized as a plurality of memory lines, and each memory line includes a memory location from each memory bank,

wherein said address generator unit is adapted to generate write addresses to the plurality of memory banks to write the rearranged first data objects to the plurality of memory banks during the first operating mode, such that the first data objects are stored in separate memory lines, and

wherein said address generator unit is adapted to generate read addresses to the plurality of memory banks to simultaneously and separately read the plurality of first data items, each from a different one of the first data objects, during the first operating mode.

12. A data store apparatus as claimed in claim 1, wherein said encoder unit comprises a rotating unit for rotating an order of the plurality of first data items of the first data objects during the first operating mode.

13. A data store apparatus as claimed in claim 1, wherein said decoder unit comprises a rotating unit for rotating an order of the plurality of read first data items.

14. A data store apparatus for storing first data objects comprised of a plurality of first data items and for storing second data objects comprised of one or more second data items, said apparatus comprising:

a first rearrangement unit for rearranging an order of the plurality of first data items of the first data objects in accordance with a first rearranging mode, and for outputting the rearranged first data objects;

a storage unit comprising a plurality of separately addressable memory banks, said storage unit organized as a plurality of memory lines with each memory line including a memory location from each memory bank;

a write unit for writing the rearranged first data objects in the plurality of memory banks in accordance with a first write mode, such that the first data objects are stored in separate memory lines, and for writing the second data objects in the plurality of memory banks in accordance with a second write mode;

a read unit for simultaneously and separately reading the plurality of first data items, each from a different one of the first data objects, from the plurality of memory banks in accordance with a first read mode, and for reading the one or more second data items from the plurality of memory banks in accordance with a second read mode;

a second rearrangement unit for rearranging an order of the plurality of read first data items in accordance with a second arranging mode; and

a controller unit for generating control signals for controlling the first and second rearranging modes, the first and second write modes, and the first and second read modes.

15. A data store apparatus as claimed in claim 14, wherein said first rearrangement unit comprises a rotating unit for rotating the order of the plurality of first data items of the first data objects.

16. A data store apparatus as claimed in claim 14, wherein said second rearrangement unit comprises a rotating unit for rotating the order of the plurality of read first data items.

17. A data store apparatus as claimed in claim 14, wherein said first rearrangement unit comprises a plurality of logic circuits.

18. A data store apparatus as claimed in claim 14, wherein said read unit comprises a read address multiplexer unit for multiplexing incoming read addresses to internal read addresses for the plurality of memory banks.

19. A data store apparatus as claimed in claim 14, wherein said second rearrangement unit comprises a plurality of logic circuits.

20. A data store apparatus as claimed in claim 14, wherein said read unit comprises a plurality of logic circuits for calculating memory read addresses for said storage unit.

21. A data store apparatus as claimed in claim 14, wherein said write unit comprises a plurality of logic circuits for calculating memory write addresses supplied to said storage unit.

22. A data store apparatus as claimed in claim 14, wherein said controller unit comprises a plurality of logic circuits for generating the control signals.

23. A data store apparatus as claimed in claim 14, wherein said apparatus is utilized for storing pixel data and retrieving single color component data for minimum coded unit decomposition during a JPEG compression operation.

24. A data store apparatus as claimed in claim 14, wherein said apparatus is utilized for storing single color component block data and retrieving pixel data for minimum reconstruction during a JPEG decompression operation.

25. A data store apparatus as claimed in claim 14, wherein said apparatus is utilized for storing and retrieving second data objects for a color space conversion operation.

26. A data store apparatus as claimed in claim 14, wherein said apparatus is utilized for storing and retrieving matrix coefficients as second data objects for operations that involve matrix multiplication.

27. A method for storing a plurality of first data objects comprised of a plurality of first data items and for storing second data objects comprised of one or more second data items in a storage unit comprised of a plurality of separately addressable memory banks, the storage unit organized as a plurality of memory lines with each memory line including a memory location from each memory bank, said method comprising the steps of:

rearranging an order of the first data items of the first data objects in accordance with a first rearranging mode, and outputting the rearranged first data objects;

writing the rearranged first data objects in the plurality of memory banks in accordance with a first write mode, such that the first data objects are stored in separate memory lines, and writing the second data objects in the plurality of memory banks in accordance with a second write mode;

simultaneously and separately reading the plurality of first data items, each from a different one of the first data objects, from the plurality of memory banks in accordance with a first read mode, and reading the one or more second data items from the plurality of memory banks in accordance with a second read mode;

rearranging an order of the plurality of read first data items in accordance with a second arranging mode; and

generating control signals for controlling the first and second rearranging modes, the first and second write modes, and the first and second read modes.

28. A method as claimed in claim 27, wherein said first rearranging step comprises rotating an order of the plurality of first data items of the first data objects.

29. A method as claimed in claim 27, wherein said second rearranging step comprises rotating an order of the plurality of read first data items.

30. A method as claimed in claim 27, wherein said reading step comprises:

multiplexing incoming read addresses to internal read addresses for the memory banks.

31. A method as claimed in claim 27,

wherein the first data objects each comprise pixel data and the plurality of first data items each comprise single color component data of the pixel data, and

wherein said reading step of reading the plurality of first data items comprises retrieving single component data for minimum coded unit decomposition during a JPEG compression operation.

32. A method as claimed in claim 27,

wherein the first data objects each comprise a single color component block of data and the plurality of first data items each comprise single color component data of a block of data, and

wherein said reading step of reading the plurality of first data items comprises retrieving pixel data for minimum coded unit reconstruction during a JPEG decompression operation.

33. A method as claimed in claim 27, wherein the second data objects are utilized in a color space conversion operation.

34. A method as claimed in claim 27, wherein the second data objects are matrix coefficients utilized for operations that involve matrix multiplication.