Data processing circuits and interfaces

• US 6,311,263 B1
• Filed: 03/24/1997
• Issued: 10/30/2001
• Est. Priority Date: 09/23/1994
• Status: Expired due to Term

• Current Assignee: Cambridge Solutions Limited (DXC Technology Company)
• Original Assignee: Cambridge Silicon Radio Limited (Qualcomm, Inc.)
• Inventors: Barlow, Stephen John, Collier, James Digby, Morfey, Alistair Guy
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/809,498
• Time in Patent Office: 1,681 Days
• Field of Search: 710/59, 710/22, 710/61, 710/58, 710/112, 710/23, 710/129, 710/3, 710/57, 710/204, 710/242, 710/54, 710/241, 710/117, 710/45, 710/51, 710/113, 709/105, 709/234, 709/225, 709/233, 711/135, 711/138, 711/167, 711/139, 711/206, 711/100, 711/137, 711/136, 711/104, 711/152, 711/146, 711/168, 712/35, 712/31, 712/29, 712/36, 712/17, 712/30
• US Class Current: 712/36
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/3648 using additional hardware
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/322 for non-sequential address
• CPC Class Codes: G06F 9/324 using program counter relative addressing
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analogue and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. External pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test data or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SER-CLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimize power consumption.

Claims

1. A data processing apparatus including;

a processor constructed to operate under control of a stored program comprising a sequence of program instructions selected from a predetermined instruction set;

an interface circuit which is operable to provide an interface for an external apparatus to signal a request for access to one of a plurality of storage locations within the processor, said one of a plurality of storage locations being specified independently of the stored program in a communication request supplied by the external apparatus to the interface circuit; and

control means operable to cause the processor to provide access between the specified storage location and the interface circuit in response to such a communication request only at predetermined points in the execution of the stored program, said control means being operable to fix periods of time for providing such access relative to the sequence of program instructions such that execution timing of the stored program is independent of whether or not such a communication request is supplied to said interface circuit by said external apparatus.

2. An apparatus according to claim 1, wherein said control means comprises a generic communication instruction (SIF) of the instruction set, the generic communication instruction having a fixed execution time by said processor.

3. An apparatus according to claim 1, wherein the processor and stored program are provided on a single integrated circuit.

4. An apparatus according to claim 1, wherein said interface circuit is operable to provide a serial interface to the external apparatus.

5. An apparatus according to claim 4, wherein said serial interface includes separate data lines for input and output of data to the interface circuit, which allows data to be shifted serially into the interface circuit at the same time as data is being shifted serially out of the interface circuit.

6. An apparatus according to claim 5, wherein said serial interface further includes a clock line for synchronizing data input and output asynchronously with respect to operation of said processor.

7. An apparatus according to claim 1, wherein the communication request includes a specific communication instruction loaded by the external apparatus into an interface register of the interface circuit, and wherein the control means is operable to provide access between the specified storage location and the interface register under control of the specific communication instruction.

8. An apparatus according to claim 7, wherein the interface circuit includes at least one control line which has an active state which is setable by either of the interface circuit and the external apparatus, wherein said external apparatus is operable to signal said request for access by setting the active state of said at least one control line, wherein said interface circuit is operable to detect the setting of said active state of said at least one control line by said external apparatus and to maintain the active state on said at least one control line until access has been provided between the specified storage location and the interface circuit during one of said periods of time and wherein said interface circuit is operable to release said control line when it is ready to receive a subsequent communication request.

9. An apparatus as claimed in claim 8 wherein said idle state of said at least one control line is setable by said external apparatus and wherein a specific communication instruction of said subsequent communication request will not be read internally from the interface register and processed until the control line has been released by both the interface circuit and the external apparatus for a predetermined time and then again set to the active state by the external apparatus.

10. An apparatus according to claim 8, wherein, at least for a specific communication instruction which is recognized by the processor as requiring information in response, said processor is operable to load said information into the interface register of the interface circuit during said time period, before the interface circuit releases the control line, which allows said information to be read from the interface register by the external apparatus.

11. An apparatus according to claim 7, comprising circuitry which is operable to interpret the specific communication instruction in accordance with pre-determined rules.

12. An apparatus according to claim 7, wherein the processor has a basic data width of sixteen bits, and the interface register contains more than thirty bits.

13. An apparatus according to claim 7, wherein said specific communication instruction includes an address field which is interpreted by the processor as specifying said storage location within a storage space of the processor, and wherein the control means is responsive to the specific communication instruction during said time period to allow reading, writing or a selection of reading and writing to be performed between the interface circuit and the specified storage location.

14. An apparatus according to claim 13 wherein said storage space comprises data space, register space, and/or program memory of the processor.

15. An apparatus according to claim 14, wherein said processor comprises a memory access interface which is operable to distinguish between memory accesses performed under normal program control and memory accesses performed in response to the communication request.

16. An apparatus according to claim 13, wherein said specific communication instruction is a read instruction and wherein said external apparatus is operable to load an address into an address field portion of the interface register to initiate one read operation without loading the entire interface register.

17. An apparatus according to claim 13, wherein said specific communication instruction is a read instruction, wherein said interface register includes a data portion for data read from said storage location, separate from an address field portion and wherein said external apparatus is operable to read data from the data portion of the interface register to complete one read operation without reading out the entire interface register.

18. An apparatus according to claim 13, wherein said specific communication instruction is a read instruction, wherein said interface register includes a data portion for data read from said storage location, separate from an address field portion and said interference register is arranged to allow the external apparatus to read data from the data portion of the interface register to complete one read operation while an address is being loaded into the address field portion of the interface register to initiate another read operation.

19. An apparatus according to claim 13, wherein said external apparatus is operable to select a reading or writing operation within the processor under control of a selection field in the specific communication instruction loaded into the interface register.

20. An apparatus according to claim 13, wherein said interface register is a shift register which is loadable bit-serially under control of said external apparatus.

21. An apparatus according to claim 20, wherein said interface register includes a separate data portion and address portion, and wherein said address portion is nearer than the data portion to an input end of the shift register.

22. An apparatus according to claim 21, wherein said shift register further includes a read/write selection portion nearer than the data portion to the input end of the shift register.

23. An apparatus according to claim 1, wherein the processor is responsive to a predetermined external signal so as to enter a state in which program controlled operation of the processor is suspended, and wherein said control means is responsive to received communication requests to provide said access at any time during said suspended state.

24. An apparatus according to claim 1, wherein said processor has no interrupt handling facility.

25. An apparatus according to claim 1, further comprising mixed analogue and digital signal processing circuitry integrated with said processor in a single integrated circuit.

26. An apparatus according to claim 1, wherein address lines and read/write select line within the processor are operable to carry address and selection signals for accessing said storage locations, and wherein said control means is operable to select, for application to said aess and said read/write select line, either address and selection signals generated by addressing means of the processor, or, during said periods of time, address and selection signals supplied by the interface circuit.

27. An apparatus according to claim 1, wherein said processor comprises:

an instruction decoding circuit for implementing control within the processor in accordance with the stored program;

an arithmetic unit having input and output data paths of width n bits;

a register of width greater than n bits connectable under control of the instruction decoding circuit to at least one of the input and output paths of the arithmetic unit; and

a shifting circuit separate from the arithmetic unit for performing shift operations of said greater width using said register.

28. An apparatus according to claim 27 wherein said instruction decoding circuit is responsive to a predetermined division instruction to control the arithmetic unit, the shifting circuit and the register so as to divide two values of width n bits, the quotient and remainder being obtained in the register.

29. An apparatus according to claim 28, wherein the division operation is performed over plural operating cycles of the arithmetic unit and the shifting circuit.

30. An apparatus according to claim 27, wherein the shifting circuit is operable to perform only single bit position shifting per operating cycle.

31. An apparatus according to claim 27, wherein dedicated unidirectional data paths are provided (i) between the register output and the input path of the arithmetic unit and (ii) between the arithmetic unit output and the register input.

32. An apparatus according to claim 27, comprising at least one external control line, and wherein at least one instruction of the instruction set is decoded differently by said decoding circuit depending on a signal present on the external control line.

33. An apparatus according to claim 27, wherein the processor has a basic instruction cycle sub-divide into plural internal clock states, and wherein, for at least one combinational logic circuit having plural input lines and functioning under control of each stored program, means are provided to sample and latch input values for the combinational logic circuit only at a defined state or states within the operational cycle.

34. An apparatus according to claim 33, wherein said combinational logic circuit comprises the arithmetic unit of the processor.

35. An apparatus according to claim 34, wherein said combinational logic circuit further comprises the instruction decoding circuit of the processor.

36. An apparatus according to claim 27, wherein said shifting circuit is physically connected between the output path of the arithmetic unit and data inputs of said register, with feedback also from data outputs of said register.

37. An apparatus according to claim 27, wherein said register of greater width comprises a pair of registers each of width n, independently connectable to an input or output path of said arithmetic unit.

38. An apparatus according to claim 27, wherein said instruction decoding circuit is responsive to a predetermined multiplication instruction to control the arithmetic unit, the shifting circuit and the register so as to multiply two values of width n bits, the result being obtained in the register.

39. An apparatus according to claim 38, wherein the multiplication operation is performed over plural operating cycles of the arithmetic unit and the shifting circuit.

40. An apparatus according to claim 1, wherein the execution of each program instruction takes a number of processor execution cycles, dependent on the type of instruction, and wherein a further instruction is not executable until a current instruction has been completely executed.

41. An apparatus according to claim 1, wherein said processor comprises:

an instruction decoding circuit for implementing control within the processor in accordance with the stored program;

an arithmetic unit having input and output data paths of width n bits;

a register space of width n bits connectable under control of the instruction decoding circuit to either the input or output paths of the arithmetic unit,

wherein dedicated unidirectional data paths are provided (i) between the register space output(s) and the input path of the arithmetic unit and (ii) between the arithmetic unit output path and the input(s) of the register space.

42. An apparatus according to claim 41, wherein a further dedicated path is provided from a program counter register to one data register of the processor for storing a subroutine return address said data path including an incrementer.

43. An apparatus according to claim 1, further comprising means for implementing a state of low power consumption in which execution of said program by said processor is suspended, and means for ending said suspended state so that execution of said program continues from the next instruction in the stored sequence without execution of instructions stored outside said sequence.

44. An apparatus according to claim 43, wherein said suspended state is entered in response to a signal applied to the processor, but only at a time in the instruction sequence defined by inclusion of a specific instruction.

45. An apparatus according to claim 43, wherein said suspended state is entered in response to a sleep instruction which forms part of said stored program.

46. An apparatus according to claim 1, further comprising:

means for imposing a state of low power consumption in which execution of said stored program by said processor is suspended and in which a clock signal for said processor is isolated from the processor, while the clock signal continues running; and

monitoring means responsive to any of a plurality of external signals for ending said suspended state by reapplying said clock signal to the processor, wherein said monitoring means comprises;

plural individual monitoring circuits for detecting predetermined changes in respective ones of the external signals; and

a common trigger circuit responsive to outputs of the individual monitoring circuits for re-applying said clock signal to the processor,

and wherein the individual monitoring circuits, but not the common trigger circuit, are isolated from the running clock signal during said suspended state.

47. An apparatus according to claim 46, wherein at least one of said individual monitoring circuits comprises:

means responsive to said clock signal prior to the suspended state for storing a value of the corresponding external signal; and

asynchronous circuit means for, during the suspended state, comparing the external signal with the stored value.

48. An apparatus according to claim 46, wherein said read or write operation is performed without interpretation by said processor.

49. An apparatus according to claim 1, wherein the apparatus has at least one external control line, and wherein at least one instruction of the instruction set is an instruction which will either halt the execution of the stored program or will effect no meaningful operation, depending on a signal applied to said external control line.

50. An apparatus according to claim 49, comprising means for signaling externally that execution has been halted.

51. An apparatus according to claim 49 comprising at least one further external control line and wherein said apparatus is responsive to signals applied to said control lines so as to:

(I) start and stop the execution of the stored program;

(ii) to halt the execution of the stored program at a predetermined instruction;

or (iii) to single step through the sequence of program instructions of said stored program.

52. In combination, a data processing apparatus and an external apparatus, the data processing apparatus including:

a processor constructed to operate under control of a stored program comprising a sequence of program instructions selected from a predetermined instruction set;

an interface circuit which is operable to provide an interface for the external apparatus to signal a request for access to one of a plurality of storage locations within the processor, said one of a plurality of storage locations being specified independently of the stored program in a communication request supplied by the external apparatus to the interface circuit; and

control means comprising (i) means operable to provide fixed periods of time during an execution timing of the stored program by the processor during which said processor does not access said storage locations under control of said stored program, said fixed periods being provided at predetermined points in the execution of the stored program; and

(ii) means operable to cause the processor to provide access between the specified storage location and the interface circuit in response to such a communication request only during said fixed periods of time whereby the execution timing of the stored program by the processor is independent of whether or not such a communication request is supplied to said interface circuit by said external apparatus.

53. The combination of claim 52, wherein said communication request includes a read instruction loaded by the external apparatus into an interface register of the interface circuit, which interface register includes a data portion for data read from said storage location, separate from an address field portion and wherein said external apparatus is operable to read data from the data portion of the interface register to complete one read operation without having to read out data from the entire data portion of the interface register.

54. A data processing apparatus including:

input means for receiving input data;

a processor operable to process the input data in accordance with a stored program comprising a sequence of program instructions selected from a predetermined instruction set and using a plurality of storage locations within the processor;

an interface circuit for providing an interface for an external apparatus to signal a request for access to one of said plurality of storage locations within the processor, said one of a plurality of storage locations being specified independently of the stored program in a communication request supplied by the external apparatus to the interface circuit; and

control means comprising (i) means operable to provide fixed periods of time during an execution timing of the stored program by the processor during which said processor does not access said storage locations under control of said stored program, said fixed periods being provided at predetermined points in the execution of the stored program; and

(ii) means operable to cause the processor to provide access between the specified storage location and the interface circuit in response to such a communication request only during said fixed periods of time whereby the execution timing of the stored program by the processor is independent of whether or not such a communication request is supplied to said interface circuit by said external apparatus.

55. A data processing apparatus including:

a processor constructed to operate under control of a stored program comprising a sequence of program instructions selected from a predetermined instruction set;

an interface circuit which is operable to provide an interface for an external apparatus to signal a request for access to one of a plurality of storage locations within the processor, said one of a plurality of storage locations being specified independently of the stored program in a communication request supplied by the external apparatus to the interface circuit; and

a controller operable to provide fixed periods of time during an execution timing of the stored program by the processor during which said processor does not access said storage locations under control of said stored program, said fixed periods being provided at predetermined points in tie execution of the stored program, the controller also being operable to cause the processor to provide access between the specified storage location and the interface circuit in response to such a communication request only during said fixed periods of time whereby the execution timing of the stored program by the processor is independent of whether or not such a communication request is supplied to said interface circuit by said external apparatus.