Method for encoding/decoding digital data by using shuffling in digital video home system

• US 6,311,304 B1
• Filed: 12/30/1998
• Issued: 10/30/2001
• Est. Priority Date: 12/30/1997
• Status: Expired due to Fees

• Current Assignee: Dongbu Daewoo Electronics Corporation (Dayou Holdings Co.,Ltd.)
• Original Assignee: Daewoo Electronics Company Limited (Dayou Holdings Co.,Ltd.)
• Inventors: Kwon, Bong-Hyen
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): TORRES, JOSEPH D
• Application Number:
  US09/222,922
• Time in Patent Office: 1,035 Days
• Field of Search: 714/756, 714/701, 714/762, 714/755
• US Class Current: 714/755
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2903 Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/2909 Product codes

Abstract

A method for error correction coding (ECC) by using shuffling of a digital data supplied as a bit stream in a digital-video home system. Three methods are suggested for error correction coding/decoding. One method is where an outer ECC process for 18 ECC blocks is performed earlier than an inner ECC process for the 18 ECC blocks. Another method is where an outer ECC process and an inner ECC process for an ECC block are carried out sequentially and implemented in order for 18 ECC blocks. These two methods employ a predetermined shuffling algorithm. The third method is where an outer ECC process is firstly performed for 18 ECC blocks by using the shuffling algorithm, and then an inner ECC process is implemented by the sync block according to a recording order on tracks. The outer parity information is produced by processing the data from the shuffled sync block.

Claims

1. A method for error correction coding (ECC) by using shuffling of a digital data supplied as a bit stream in a digital-video home system, comprising the steps of:

(A) adding outer parity information to a main data of the digital data by;

i) storing the main data constituting a frame to which a track number and a sync block number are designated in a storing means, wherein the frame includes 18 ECC blocks and each ECC block includes 102 sync blocks;

ii) setting values of parameters t, g, s and VSB as 0, wherein the parameters t, g, s, and VSB respectively represent a number for tracks constituting the frame, a number for logical ECC blocks belonging to a track, a number for bytes of data constituting a vertical sync block within the ECC block, and a number for the vertical sync blocks constituting a ECC block;

iii) calculating a track number TR and a sync block number SB by using equation (1), which is TR=[t+(s×

5)] mod 6 and SB=g+s×

3, while increasing a value of the parameter s by 1 from 0 to 101 and forming a vertical sync block by shuffle-reading by the byte the main data from a sync block which corresponds to the calculated track number TR and sync block number SB;

iv) producing a predetermined byte of the outer parity information for error correction by using a predetermined polynomial with respect to the vertical sync block, and shuffle-writing by the byte the outer parity information at a location of the track number TR and the sync block number SB, which are calculated from the equation (1), in the storing means, while increasing a value of the parameter s by 1 from 102 to 111;

v) performing recursively substeps iii) and iv) while increasing a value of the parameter VSB by 1 from 0 to 98 and resetting the parameter s as 0 at every increment;

vi) performing recursively steps iii), iv) and v) while increasing a value of the parameter g by 1 from 0 to 2 and resetting the parameters s and VSB as 0 at every increment; and

vii) performing recursively the substeps iii), iv), v) and vi) while increasing a value of the parameter t by 1 from 0 to 5 and resetting the parameters s, VSB and g as 0 at every increment, wherein the outer parity information with respect to the main data of one frame is produced by shuffling through substeps i) to vii), and the produced outer parity information is written in the storing means by shuffling; and

(B) adding inner parity information to the main data and the outer parity information of the digital data by;

a) setting values of parameters t, g, P, and HSB as 0, wherein the parameters P and HSB respectively represent a number for bytes of a sync block of the main data and the outer parity information and a number for horizontal sync blocks belonging to the ECC block of the main data and the outer parity information;

b) calculating a track number TR and a sync block number SB by using equation (2), which is TR=[t+(HSB×

5)] mod 6 and SB=g+HSB×

3, while increasing a value of the parameter P by 1 from 0 to 98 and forming a horizontal sync block by reading by the byte the main data and the outer parity information from a sync block which corresponds to the calculated track number TR and sync block number SB;

c) producing a predetermined byte of the inner parity information for error correction of the horizontal sync block by using a predetermined polynomial, and writing the outer parity information by the byte at a location of the track number TR and the sync block number SB, which are calculated from equation (2), in the storing means, while increasing a value of the parameter P by 1 from 99 to 106;

d) performing recursively substeps b) and c) while increasing a value of the parameter HSB by 1 from 0 to 111 and resetting the parameter P as 0 at every increment;

e) performing recursively substeps b), c) and d) while increasing a value of the parameter g by 1 from 0 to 2 and resetting the parameters P and HSB as 0 at every increment; and

f) performing recursively substeps b), c), d) and e) while increasing a value of the parameter t by 1 from 0 to 5 and resetting the parameters P, HSB and g as 0 at every increment, wherein the inner parity information with respect to the frame of the main data and the outer parity information is produced through substeps a) to f), and the produced inner parity information is written in the storing means.

2. The method as claimed in claim 1, further comprising the step of decoding for error correction by using the outer parity information and the inner parity information after reading out encoded data on a recording medium and storing the encoded data in the storing means, wherein an error correction decoding using the inner parity information is firstly performed for the 18 ECC blocks, an error correction decoding using the outer parity information of the 18 ECC blocks is secondly performed, a data processing order for the error correction decoding by using the inner parity information is the same as a data processing order for producing of the inner parity information, and a data processing order for the error correction decoding by using the outer parity information is the same as a data processing order for producing the outer parity information.

3. A method for error correction coding (ECC) by using shuffling of a digital data supplied as a bit stream in a digital-video home system, comprising the steps of:

(A) adding outer parity information to main data of the digital data by;

i) storing the main data constituting a frame to which a track number and a sync block number are designated in a storing means, wherein the frame includes 18 ECC blocks and each ECC block includes 102 sync blocks;

ii) setting values of parameters t, g, s and VSB as 0, wherein the parameters t, g, s, and VSB respectively represent a number for tracks constituting the frame, a number for logical ECC blocks belonging to a track, a number for bytes of data constituting a vertical sync block within the ECC block, and a number for the vertical sync blocks constituting a ECC block;

iii) calculating a track number TR and a sync block number SB by using equation (1), which is TR=[t+(s×

5)] mod 6 and SB=g+s×

3, while increasing a value of the parameter s by 1 from 0 to 101 and forming a vertical sync block by shuffle-reading by the byte the main data from a sync block which corresponds to the calculated track number TR and sync block number SB;

iv) producing a predetermined byte of the outer parity information for error correction by using a predetermined polynomial with respect to the vertical sync block, and shuffle-writing by the byte the outer parity information at a location of the track number TR and the sync block number SB, which are calculated from the equation (1), in the storing means, while increasing a value of the parameter s by 1 from 102 to 111;

v) performing recursively substeps iii) and iv) while increasing a value of the parameter VSB by 1 from 0 to 98 and resetting the parameter s as 0 at every increment;

vi) performing recursively steps iii), iv) and v) while increasing a value of the parameter g by 1 from 0 to 2 and resetting the parameters s and VSB as 0 at every increment; and

vii) performing recursively the substeps iii), iv), v) and vi) while increasing a value of the parameter t by 1 from 0 to 5 and resetting the parameters s, VSB and g as 0 at every increment, wherein the outer parity information with respect to the main data of one frame is produced by shuffling through substeps i) to vii), and the produced outer parity information is written in the storing means by shuffling; and

(B) adding inner parity information to the main data and the outer parity information of the digital data by;

a) sequentially reading out in a stored order the main data and the outer parity information constituting the 18 ECC blocks by the sync block from the storing means;

b) producing a predetermined byte of the inner parity information for the error correction by using the predetermined polynomial;

c) additionally storing the produced inner parity information at a location of the storing means which corresponds to calculated track number and sync block number; and

d) iteratively performing substeps a), b) and c) until the inner parity information for the frame of main data and the outer parity information is completely produced.

4. The method as claimed in claim 3, further comprising the step of decoding for error correction by using the outer parity information and the inner parity information after reading out encoded data on a recording medium and storing the encoded data in the storing means, wherein an error correction decoding using the inner parity information is firstly performed for the 18 ECC blocks, an error correction decoding using the outer parity information of the 18 ECC blocks is secondly performed, a data processing order for the error correction decoding by using the inner parity information is the same as a data processing order for producing of the inner parity information, and a data processing order for the error correction decoding by using the outer parity information is the same as a data processing order for producing the outer parity information.

5. A method for error correction coding (ECC) by using shuffling of a digital data supplied as a bit stream in a digital-video home system, comprising the steps of:

i) storing main data constituting a frame to which a track number and a sync block number are designated in a storing means, wherein the frame includes 18 first stage ECC blocks and a first stage ECC block includes 102 sync blocks;

ii) producing outer parity information of the first ECC block by shuffling, additively storing the produced outer parity information in the first ECC block, and producing a second ECC block further including the outer parity information, said step ii) including the substeps of;

a) setting values of parameters t, g, s and VSB as 0, wherein the parameters t, g, s, and VSB respectively represent a number for tracks constituting the frame, a number for logical ECC blocks belonging to a track, a number for bytes of data constituting a vertical sync block within the ECC block, and a number for the vertical sync blocks constituting a ECC block;

b) calculating a track number TR and a sync block number SB by using equation (1), which is TR=[t+(s×

5)] mod 6 and SB=g+s×

3, while increasing a value of the parameter s by 1 from 0 to 101 and forming a vertical sync block by shuffle-reading by the byte the main data from a sync block which corresponds to the calculated track number TR and sync block number SB;

c) producing a predetermined byte of outer parity information for error correction by using a predetermined polynomial with respect to the vertical sync block, and shuffle-writing by the byte the outer parity information at a location of the track number TR and the sync block number SB in the storing means, which are calculated from equation (1) while increasing a value of the parameter s by 1 from 102 to 111; and

d) performing recursively substeps b) and c) while increasing a value of the parameter VSB by 1 from 0 to 98 and resetting the parameter s as 0 at every increment;

iii) producing inner parity information of a predetermined number of a sync block belonging to the second ECC block, adding the inner parity information to the second ECC block, and thereby producing a third ECC block of the main data including the outer parity information and the inner parity information, said step iii) including the steps of;

e) setting values of the parameters t, g, P and HSB as 0, wherein the parameters P and HSB respectively represent the number of bytes within 1 sync block of the main data and the outer parity information and the number of horizontal sync blocks belonging to 1 ECC block of the main data and the outer parity information;

f) calculating a track number TR and a sync block number SB by using equation (2), which is TR=[t+(HSB×

5)] mod 6 and SB=g+HSB×

3, while increasing a value of the parameter P by 1 from 0 to 98 and forming a horizontal sync block by reading by the byte the main data and the outer parity information from a sync block which corresponds to the calculated track number TR and sync block number SB;

g) producing a predetermined byte of inner parity information for error correction by using a predetermined polynomial of the horizontal sync block, and writing the outer parity information by the byte at a location of the track number TR and the sync block number SB, which are calculated from equation (2) in the storing means, while increasing a value of the parameter P by 1 from 99 to 106; and

h) performing recursively substeps f) and g) while increasing a value of the parameter HSB by 1 from 0 to 111 and resetting the parameter P as 0 at every increment; and

iv) successively performing steps ii) and iii) 18 times to produce outer parity information and inner parity information for the frame main data, which are additionally stored in the storing means.

6. The method as claimed in claim 5, further comprising the step of decoding for error correction by using the outer parity information and the inner parity information after reading out encoded data on a recording medium and storing the encoded data in the storing means, wherein an error correction decoding cycle, where error correction decoding by using the inner parity information is firstly performed for ECC block and an error correction decoding by using the outer parity information of the same ECC block is secondly performed, is iteratively performed 18 times to correct an error of the frame, and wherein a data processing order for the error correction decoding by using the inner parity information is the same as a data processing order for producing the inner parity information and a data processing order for the error correction decoding by using the outer parity information is the same as a data processing order for producing the outer parity information.