High speed trench DMOS

• US 6,312,993 B1
• Filed: 02/29/2000
• Issued: 11/06/2001
• Est. Priority Date: 02/29/2000
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): BERRY, RENEE R
• Application Number:
  US09/515,749
• Time in Patent Office: 616 Days
• Field of Search: 438/232, 438/301, 438/308, 438/270, 257/327, 257/328, 257/335, 257/342
• US Class Current: 438/270
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.

Claims

1. A method for forming a trench DMOS, comprising the steps of:

providing an article comprising a substrate of a first conductivity type and a body region of a second conductivity type, said article having a trench which extends through said body region and said substrate;

depositing a gate oxide layer in the trench;

forming a gate in the trench, said gate having at least one layer comprising a material selected from the group consisting of polycide and refractory metals; and

forming a source region in the body region;

wherein the source region is formed after the gate oxide layer is deposited.

2. The method of claim 1, wherein said gate comprises a first layer comprising undoped polysilicon, a second layer comprising doped polysilicon, and a third layer comprising a material selected from the group consisting of polycide and refractory metals.

3. The method of claim 2, wherein said first layer is adjacent to said gate oxide layer.

4. The method of claim 1, wherein said gate has at least one layer comprising a refractory metal.

5. The method of claim 4, wherein said refractory metal is selected from the group consisting of W and TiW.

6. The method of claim 1, wherein said gate has at least one layer comprising polycide.

7. The method of claim 6, wherein said polycide is selected from the group consisting of WSi₂ and TiSi₂.

8. The method of claim 1, wherein said trench is formed by providing a masking layer defining at least one trench, and forming the trench defined by the masking layer.

9. The method of claim 8, wherein said masking layer is disposed on said body region before said trench is formed.

10. The method of claim 8, wherein said mask is removed after said trench is formed.

11. The method of claim 1, wherein said body region is a P-body.

12. The method of claim 1, wherein said body region is formed by implanting and diffusing a dopant into the substrate.

13. The method of claim 1, wherein the body region is disposed on said substrate.

14. The method of claim 1, wherein the source region is a source region of said first conductivity type.

15. The method of claim 14, further comprising the step of forming a source region of a third conductivity type.

16. The method of claim 15, wherein the first conductivity type is n+ and the third conductivity type is p+.

17. The method of claim 1, wherein said source region is an n+ source region.

18. The method of claim 1, wherein said source region is adjacent to said trench.

19. The method of claim 1, wherein said source region is formed with a junction depth of less than about 0.5 μ

m.

20. The method of claim 1, wherein said source region is formed with a junction depth within the range of about 0.2 to about 0.5 μ

m.

21. The method of claim 1, further comprising the step of:

forming a patterned BPSG layer over said trench.

22. The method of claim 21, wherein the pattered BPSG layer is formed over the trench with a flow temperature cycle ranging from about 900 to about 950°

C.

23. The method of claim 1, wherein the step of forming a gate in the trench includes the steps of filling the trench with polysilicon, and depositing on the polysilicon a layer comprising a material selected from the group consisting of polycide and refractory metals.

24. A method for making a trench DMOS, comprising the steps of:

providing a substrate of a first conductivity type;

forming a body region on the substrate, said body region having a second conductivity type;

forming a masking layer defining at least one trench;

forming the trench defined by the masking layer, said trench extending through the body region and the substrate;

forming a gate in the trench, said gate comprising a first layer comprising undoped polysilicon, a second layer comprising doped polysilicon, and a third layer comprising a material selected from the group consisting of polycide and refractory metals; and

forming a first source region of the first conductivity type in the body region adjacent to the trench.

25. The method of claim 24, further comprising the step of:

forming a second source region of a third conductivity type adjacent to said first source region.

27. The method of claim 24, wherein said trench is covered with an insulating layer before said gate is formed.

28. The method of claim 27, wherein said insulating layer is a gate oxide layer.

26. The method of claim wherein said first source region is an n+ source, and wherein said second source region is a p+ source.

29. A method for forming a trench DMOS transistor cell, comprising the steps of:

providing an article comprising a substrate of a first conductivity type and a body region of a second conductivity type, said article having a trench which extends through said body region and said substrate;

forming a gate overlying said trench and said body region, said gate having at least one layer comprising a material selected from the group consisting of polycide and refractory metals;

placing a mask over the trench;

removing the unmasked portions of the gate; and

forming a first source region in the body region.

30. The method of claim 29, wherein the trench and body region are lined with an insulating layer prior to formation of the gate.

31. The method of claim 29, wherein the first source region is of the first conductivity type.

32. The method of claim 29, wherein the first source region is adjacent to the trench.

33. The method of claim 29, further comprising the step of:

forming a second source region of a third conductivity type.

34. The method of claim 29, wherein the first source region is an n+ source region.

35. The method of claim 33, wherein the first source region is an n+ source region, and wherein the second source region is a p+ source region.

36. The method of claim 29, wherein the step of forming the gate includes the steps of filling the trench with polysilicon, and depositing on the polysilicon a layer comprising a material selected from the group consisting of polycide and refractory metals.