Test and burn-in apparatus, in-line system using the test and burn-in apparatus, and test method using the in-line system

• US 6,313,652 B1
• Filed: 12/22/1998
• Issued: 11/06/2001
• Est. Priority Date: 12/26/1997
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Maeng, Ju Seok
• Primary Examiner(s): Karlsen, Ernest
• Assistant Examiner(s): TANG, MINH NHUT
• Application Number:
  US09/219,241
• Time in Patent Office: 1,050 Days
• Field of Search: 324/158.1, 324/755, 324/760, 324/765, 324/754, 209/574, 209/573, 209/571
• US Class Current: 324/750.05
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 31/2849 Environmental or reliability testing, e.g. burn-in or validation tests of individual semiconductors G01R31/2642; of printed circuits boards G01R31/2817; of IC's G01R31/2855

Abstract

A test and burn-in apparatus for semiconductor chip package devices, an in-line system which includes the test and burn-in apparatus, and a test method which employs the in-line system are provided. A test and burn-in apparatus for testing semiconductor devices allows various testing processes, including a burn-in process, to be performed at the same testing stage. The apparatus employs test trays which contain the semiconductor devices. These test trays are used throughout the in-line system so that an entire back-end process can be performed without the need for loading/unloading the semiconductor devices into and from device trays between the various tests. The test and burn-in apparatus according to this invention can therefore occupy less space than the prior art testing apparatuses. The in-line system includes multiple test and burn-in apparatuses as well as a single sorting unit which performs a composite sorting operation after all the testing processes have been performed. Furthermore, the method for testing the semiconductor devices in the in-line system includes testing the semiconductor devices in the test trays using the test and burn-in apparatus, generating a test tray map corresponding to results of the test, transferring the test trays to a different testing apparatus for a second testing and test tray map generation process, and finally sorting the semiconductor devices in the sorting unit after all testing processes have been performed based on a final sorting map created by combining the test tray maps of each of the tests. The benefits of this invention are reduced time and space requirements because neither transferring the devices to device trays between tests nor performing multiple sorting steps are required.

Claims

1. A test and burn-in apparatus, comprising:

a rail for transferring a plurality of test trays, each test tray configured to contain a plurality of semiconductor devices;

a loader for loading the test trays onto the rail;

an unloader for unloading the test trays from the rail;

a chamber through which the rail traverses, so that the semiconductor devices contained in the test trays loaded onto the rail can be subjected to a test and/or burn-in process within the chamber; and

a plurality of test heads associated with the chamber, wherein each test head is electrically connected to a corresponding test tray within the chamber in order to perform the test and/or burn-in process.

2. The test and burn-in apparatus according to claim 1, further comprising:

a main frame comprising a control unit which is capable of being electrically connected to the test heads.

3. The test and burn-in apparatus according to claim 2, wherein the main frame further comprises a coolant refrigerator unit configured to cool down the test heads for the test and/or burn-in process.

4. The test and burn-in apparatus according to claim 1, wherein the number of the test heads is four.

5. The test and burn-in apparatus according to claim 4, wherein each of the test heads is configured to perform the test and/or burn-in process for sixty-four semiconductor devices located in the corresponding test tray.

6. The test and burn-in apparatus according to claim 1, wherein each of the semiconductor devices comprises a semiconductor chip package with gull-wing leads or a chip scaled package.

7. The test and burn-in apparatus of claim 1 wherein the loader and unloader are located at opposite ends of the rail.

8. The test and burn-in apparatus of claim 1 wherein the loader and unloader are located at the same end of the rail.

9. The test and burn-in apparatus of claim 1 wherein the loader and unloader are stacked.

10. The test and burn-in apparatus of claim 1 wherein the rail has double layers.