High speed low voltage differential signal driver having reduced pulse width distortion

• US 6,313,662 B1
• Filed: 12/18/1998
• Issued: 11/06/2001
• Est. Priority Date: 07/10/1998
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ide, Satoshi
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): PAIK, STEVEN SANGYUL
• Application Number:
  US09/215,157
• Publication Number:
  US 20010040466A1
• Time in Patent Office: 1,054 Days
• Field of Search: 326/30, 326/82, 326/83, 326/86, 326/17, 326/121, 326/27
• US Class Current: 326/83
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

A driver circuit for transmitting a signal by switching the direction of a signal current which flows on a pair of transmission lines. The drains of field effect transistors having the opposite polarities are connected to each other so as to constitute first and second switches. One of differential driving signals is input to the gate terminal of each of the field effect transistors constituting the first switch, while the drain terminal is connected to one of the transmission line pair. The other of the differential driving signals is input to the gate terminal of each of the field effect transistors constituting the second switch, while the drain terminal is connected to the other of the transmission line pair.

Claims

1. A driver circuit to transmit a signal by switching the direction of a signal current which flows on a pair of transmission lines, said driver circuit comprising:

a pair of PMOS transistors as current switching elements on a high-potential side;

a pair of NMOS transistors as current switching elements on a low-potential side; and

a control signal generator to generate a positive phase control signal to drive a first PMOS transistor of said PMOS transistor pair and a first NMOS transistor of said NMOS transistor pair and to input the positive phase control signal to gates of each of said first transistors, and to generate a negative phase control signal which drives a second PMOS transistor of said PMOS transistor pair and a second NMOS transistor of said NMOS transistor pair and to input the negative phase control signal to gates of each of said second transistors,

wherein a drain of said first PMOS transistor is connected to a drain of said first NMOS transistor, and one of said transmission lines is connected to a portion at which said drains are connected to each other,

wherein a drain of said second PMOS transistor is connected to a drain of said second NMOS transistor, and the other of said transmission lines is connected to a portion at which said drains are connected to each other, and

wherein said control signal generator includes a first differential amplifier to which differential signals are input as input signals, and which outputs first differential signals to drive said PMOS transistor pair, and a second differential amplifier to which the differential signals are input and which outputs second differential signals to drive said NMOS transistor pair and outputs said positive phase control signal and said negative phase control signal from said first and second differential amplifiers.

2. A driver circuit according to claim 1, wherein

said first differential amplifier to generate said first differential signals which drive said PMOS transistor pair adopts a resistor as a load element; and,

said second differential amplifier to generate said second differential signals which drive said NMOS transistor pair adopts a resistor and a NMOS transistor with the gate and the drain connected thereto as a load element.

3. A driver circuit according to claim 2, wherein said control signal generator further includes a bias current source to constantly turn on said NMOS transistor which is used as said load element.

4. A driver circuit to transmit a signal by switching the direction of a signal current which flows on a pair of transmission lines on the basis of differential driving signals, said driver circuit comprising:

a first switch and a second switch, with the first switch having a first and second field effect transistors having opposite polarities with drains of each first and second field effect transistor being connected to each other, and with the second switch having a third and fourth field effect transistors having opposite polarities with drains of each third and fourth field effect transistor being connected to each other;

a signal generator to generate the differential driving signals wherein one of the differential driving signals is input to a gate of each of the first and second field effect transistors, and the other of the differential driving signals is input to a gate of each of the third and fourth field effect transistors;

a connection to connect drains of the first and second field effect transistors to one of said transmission line pair and to connect drains of the third and fourth field effect transistors to the other of said transmission line pair;

a constant voltage source to generate a bias voltage; and

a pair of bias resistors to respectively connect the connected first and second field effect transistor drains and the connected third and fourth field effect transistor drains to said constant voltage source.

5. A driver circuit according to claim 4, further comprising:

a first current source coupled between sources of the first and third field effect transistor and a high-potential wire, and

a second current source coupled between sources of the second and fourth field effect transistor and a low-potential wire.

6. A driver circuit to transmit a signal by switching the direction of a signal current which flows on a pair of transmission lines on the basis of differential driving signals, said driver circuit comprising:

a first switch and a second switch, with the first switch having first and second field effect transistors having opposite polarities with drains of of the first and second field effect transistors connected to each other and to a first transmission line, and with the second switch having third and fourth field effect transistors having opposite polarities with drains of the third and fourth field effect transistors connected to each other and to a second transmission line; and

a signal generator to generate the differential driving signals with one of the differential driving signals input to a gate of each of the first and second field effect transistors, and the other of the differential driving signals input to a gate of each of the third and fourth field effect transistors, said signal generator including

first and second CMOS logic circuits connected to each other in series and to receive CMOS level signals as input signals, and having outputs,

a first delay circuit connected to the output of the first CMOS logic circuit to output the one of the differential driving signals, and

a second delay circuit connected to the output of the second CMOS logic circuit to output the other of the differential driving signals, where a total delay time of the second CMOS logic circuit and the second delay circuit is equal to a delay time of the first delay circuit.

7. A driver circuit according to claim 6, further comprising:

a current source coupled between sources of the first and third field effect transistors and a high-potential wire, and

a load element coupled between sources of the second and fourth field effect transistors and a low-potential wire.

8. A driver circuit according to claim 6, further comprising:

a load element coupled between sources of the first and third field effect transistors and a high-potential wire, and

a current source coupled between sources of the second and fourth field effect transistors and a low-potential wire.

9. A driver circuit to transmit a signal by switching the direction of a signal current which flows on a pair of transmission lines on the basis of differential driving signals, said driver circuit comprising:

a first switch and a second switch, with the first switch having a first and second field effect transistors having opposite polarities with drains of each first and second field effect transistor being connected to each other, and with the second switch having a third and fourth field effect transistors having opposite polarities with drains of each third and fourth field effect transistor being connected to each other;

a signal generator to generate the differential driving signals wherein one of the differential driving signals is input to a gate of each of the first and second field effect transistors, and the other of the differential driving signals is input to a gate of each of the third and fourth field effect transistors; and

a connection to connect the drains of the first and second field effect transistors to one of said transmission line pair and connecting the drains of said third and fourth field effect transistors to the other of said transmission line pair,

wherein said signal generator includes a differential amplifier to which differential signals are input as input signals, and outputs said one of the differential driving signals and said other of the differential driving signals from said differential amplifier.

10. A driver circuit according to claim 9, wherein

said signal generator further includes a pair of source follower circuits each pair having a constant current source and a field effect transistor connected in series, in which each of the differential signals output from said differential amplifier inputs to each of the source follower circuits and the source follower circuits respectively output said one of the differential driving signals and said other of the differential driving signals.

12. A driver circuit according to claim 10, wherein

said first differential amplifier adopts a resistor as a load element;

and

said second differential amplifier adopts a resistor and a NMOS transistor with the gate and the drain connected thereto as a load element.

11. A driver circuit to transmit a signal by switching the direction of a signal current which flows on a pair of transmission lines on the basis of differential driving signals, said driver circuit comprising:

a first switch and a second switch, with the first switch having a first and second field effect transistors having opposite polarities with drains of each first and second field effect transistor being connected to each other, and with the second switch having a third and fourth field effect transistors having opposite polarities with drains of each third and fourth field effect transistor being connected to each other;

a signal generator to generate the differential driving signals wherein one of the differential driving signals is input to a gate of each of said first and second field effect transistors, and the other of the differential driving signals is input to a gate of each of the third and fourth field effect transistors; and

a connection to connect the drains of the first and second field effect transistors to one of said transmission line pair and connecting the drains of the third and fourth field effect transistors to the other of said transmission line pair,

wherein said signal generator includes a first differential amplifier to which differential signals are input as input signals and which outputs first differential signals to drive said first and third field effect transistors, and a second differential amplifier to which the differential signals are input and which outputs second differential signals to drive said second and fourth field effect transistors.

13. A driver circuit according to claim 11, wherein

said signal generator further includes a bias current source to constantly turn on said NMOS transistor which is used as said load element.