Offset cancelled integrator

• US 6,313,685 B1
• Filed: 04/05/2000
• Issued: 11/06/2001
• Est. Priority Date: 05/24/1999
• Status: Active Grant

• Current Assignee: Level One Communications, Inc. (Intel Corporation)
• Original Assignee: Level One Communications, Inc. (Intel Corporation)
• Inventors: Rabii, Shahriar
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/543,181
• Time in Patent Office: 580 Days
• Field of Search: 327/307, 327/336, 327/337, 327/362, 327/345, 327/355-361, 327/554, 327/91, 327/94-96, 327/341, 330/9
• US Class Current: 327/307
• CPC Class Codes: G06G 7/1865 with initial condition setting

Abstract

An offset integrator and method are provided to induce integrator leakage while simultaneously latching and canceling its own offset. The method includes combining a first and second input signals with a part of the output signal of a different polarity to produce a charge signal. An accumulation of the charge signal on a plurality of storage components is used to reduce the offset component of the output signal and simultaneously inducing an integrator leak. A positive and negative components of the input signals are combined with a negative and positive offset components of the part of the output signal, respectively. The method liner includes modifying a positive and negative components of an in-phase and a quadrature signal. A reset signal may be provided to erase a plurality of memory locations. A gating scheme may be used to provide a predetermined signal to produce a two-phase, non-overlapping signal. The two-phase non-overlapping signal also produces a predetermined delayed two-phase, non-overlapping signal. The gating scheme provides proper timing signals without the use of complementary clock phases.

Claims

1. An offset cancelled integrator circuit, comprising:

an arithmetic circuit receiving a plurality of input signals; and

an offset circuit having an integrating component and a latching and canceling component, coupled to the arithmetic circuit, generating a plurality of output signals and feeding back the plurality of output signals to the arithmetic circuit, the arithmetic circuit and the offset circuit being arranged and configured to induce integrator leakage by the integrating component while simultaneously latching and canceling an offset voltage by the latching and canceling component.

2. A method of canceling a DC offset in a transceiver system, comprising:

combining a first and second input signals to produce a charge signal; and

integrating via an integrating component while simultaneously latching and canceling an offset voltage from the charge signal via a latching and canceling component to generate an output signal.

3. The method of claim 2, wherein the step of integrating while simultaneously latching and canceling an offset voltage from the charge signal includes a step of reducing the charge signal using a charge reduction signal and accumulating the reduced charge signal, and wherein the step of combining includes a step of combining a positive component of the first input signal and a negative component of the second input signal with a negative component and a positive component of the charge reduction signal, respectively, wherein the first and second input signals and the charge reduction signal accumulate on a first storage component, a second storage component, and a third storage component, respectively.

4. The method of claim 3, wherein the reducing includes subtracting a sum of the first and second positive components of the input signal from the negative component of the charge reduction signal, and subtracting a sum of the first and second negative components of the input signal from the positive component of the charge reduction signal.

5. The method of claim 3, wherein the reducing includes modifying a positive component and a negative component of an in-phase signal and a quadrature signal.

6. The method of claim 3, wherein the reducing includes combining the first and second input signals with the charge reduction signal of an opposite polarity via a fourth storage component.

7. The method of claim 4, wherein the reduction of the offset component by leaking the fraction of the charge signal further includes combining the first and second input signals with the charge reduction signal of the opposite polarity via a fifth storage component.

8. The method of claim 3, wherein the accumulating of the reduced charge signal to generate the output signal further includes amplifying the positive component and the negative component of the charge signal.

9. An offset cancelled integrator circuit in a transceiver system, comprising:

an arithmetic circuit to combine a first and second input signals to produce a charge signal having an offset; and

an offset circuit having an integrating component and a latching and canceling component, coupled to the arithmetic circuit, to reduce the charge signal to produce a reduced charge signal, the reduced charge signal being produced by using a charge reduction signal to leak a fraction of the charge signal by the latching and canceling component and simultaneously accumulating the reduced charge signal by the integrating component to produce an output signal.

10. The offset cancelled integrator circuit of claim 9, wherein the arithmetic circuit includes a plurality of storage components for combining a positive component and a negative component of the input signal with a negative component and a positive component of the charge reduction signal, respectively.

11. The offset cancelled integrator circuit of claim 10, wherein the storage components further combine the sum of the first and second positive components of the input signal with the negative component of the charge reduction signal, and combine the sum of the first and second negative components of the input signal with the positive component of the charge reduction signal.

12. The offset cancelled integrator circuit of claim 11, wherein the first and second input signals and the charge reduction signal accumulate on a first storage component, a second storage component, and a third storage component, respectively.

13. The offset cancelled integrator circuit of claim 12, wherein the offset circuit further includes a fourth storage component for accumulating the resulting sum of the first and second input signals and the charge reduction signal of an opposite polarity.

14. The offset cancelled integrator circuit of claim 13, wherein the offset circuit further includes a fifth storage component for leaking a fraction of the charge signal by combining the resulting sum of the first and second input signals and the charge reduction signal of the opposite polarity.

15. The offset cancelled integrator circuit of claim 10, wherein the storage components are capacitors.