Bias network for high efficiency RF linear power amplifier

• US 6,313,705 B1
• Filed: 12/20/1999
• Issued: 11/06/2001
• Est. Priority Date: 12/20/1999
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Dening, David C., Jorgenson, Jon D.
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/467,415
• Time in Patent Office: 687 Days
• Field of Search: 330/285, 330/288, 330/296, 330/289
• US Class Current: 330/276
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal

Abstract

A bias network uses resistive biasing, active biasing and current mirror biasing in combination to enhance RF power amplifier linearity and efficiency by forming a bias network that provides temperature compensation, minimizes current drain requirements for the Vbias source and reduces the level of RF linear amplifier quiescent current.

Claims

1. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

a buffered passive bias network having a first bipolar junction transistor and further having an emitter resistor associated with the first bipolar junction transistor; and

a current mirror bias network coupled to the buffered passive bias network, the current mirror bias network having a second bipolar junction transistor and further having a collector resistor and a base resistor associated with the second bipolar junction transistor;

wherein a combination of resistance values for the emitter, base and collector resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

2. The linear amplifier bias network according to claim 1 further comprising an inductor having a first end coupled to a ground node and further having an opposite end coupled to the emitter of the second bipolar junction transistor such that the emitter of the second bipolar junction transistor is coupled to the ground node solely through the inductor.

3. The linear amplifier bias network according to claim 2 wherein any single resistor selected from the group consisting of the emitter resistor, the collector resistor and the base resistor is configured to have zero resistance.

4. The linear amplifier bias network according to claim 1 further comprising:

a supply voltage node;

a ground node;

a diode network; and

a resistor having a first end coupled to the supply voltage node and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

5. The linear amplifier bias network according to claim 4 wherein the diode network includes a plurality of diodes and a series resistor.

6. The linear amplifier bias network according to claim 5 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the diode network such that a portion of the diode network is coupled to the ground node solely through the inductor.

7. The linear amplifier bias network according to claim 6 wherein any single resistor selected from the group consisting of the emitter resistor, the collector resistor and the base resistor is configured to have zero resistance.

8. The linear amplifier bias network according to claim 1 further comprising:

a supply voltage node;

a ground node;

a transistor network configured as a diode network; and

a resistor having a first end coupled to the supply voltage node and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

9. The linear amplifier bias network according to claim 8 wherein the transistor network includes a plurality of bipolar junction transistors and a series resistor.

10. The linear amplifier bias network according to claim 9 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

11. The linear amplifier bias network according to claim 10 wherein any single resistor selected from the group consisting of the emitter resistor, the collector resistor and the base resistor is configured to have zero resistance.

12. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

a buffered passive bias network having a first bipolar junction transistor and further having at least one emitter resistor associated with the first bipolar junction transistor; and

a current mirror bias network coupled to the buffered passive bias network, the current mirror bias network having a second bipolar junction transistor and further having at least one emitter inductor associated with the second bipolar junction transistor;

wherein a combination of impedance values for the at least one emitter resistor and at least one emitter inductor are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.

13. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having a first end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

an active bias network having a first bipolar junction transistor and a base resistor;

means for establishing an impedance in the emitter leg of the first bipolar junction transistor to achieve a desired level of quiescent bias current associated with the radio frequency bipolar junction transistor, wherein the means for establishing the impedance is independent of the base resistor;

first means for establishing an impedance for the linear amplifier bias network to achieve a desired first temperature compensation characteristic wherein the first means for establishing an impedance for the linear amplifier bias network is independent of the means for establishing an impedance in the emitter leg of the first bipolar junction transistor and is further independent of the base resistor; and

second means for establishing an impedance for the linear amplifier bias network to achieve a desired second temperature compensation characteristic wherein the second means for establishing an impedance for the linear amplifier bias network is independent of the first means and the means for establishing an impedance in the emitter leg of the first bipolar junction transistor and is further independent of the base resistor.

14. The linear amplifier bias network according to claim 13 wherein the second means comprises a bipolar junction transistor having a base, a collector and an emitter, and further comprising an inductor having a first end coupled to the emitter of the bipolar junction transistor and having an opposite end coupled to a ground.