Analog phase locked loop holdover

• US 6,313,708 B1
• Filed: 07/26/2000
• Issued: 11/06/2001
• Est. Priority Date: 07/26/2000
• Status: Expired due to Fees

• Current Assignee: Marconi Intellectual Property (Ringfence), Inc. (Marconi Holdings Company Limited)
• Original Assignee: Marconi Communications, Inc. (Marconi Holdings Company Limited)
• Inventors: Beaulieu, Rejean
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US09/625,698
• Time in Patent Office: 468 Days
• Field of Search: 331/1.A, 331/8, 331/14, 331/17, 331/18, 331/25, 331/DIG.2, 327/156-159, 360/51, 375/376, 455/260
• US Class Current: 331/17
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H03L 7/146 by using digital means for generating the oscillator control signal H03L7/141, H03L7/143 take precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase locked loop (PLL) circuit is provided having: (1) a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal; (2) an integrator coupled to the positive and negative phase detection signals for generating an output voltage proportional to the pulse width of either the positive or negative phase detection signals, the integrator including an operational amplifier having positive and negative inputs; (3) a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator; (4) a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and (5) an analog holdover circuit for generating an input to the integrator when the phase detector stops receiving the reference clock signal.

Claims

1. A phase locked loop, comprising:

a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal;

an integrator coupled to the positive and negative phase detection signals for generating an output voltage in response to pulses from the phase detector;

a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator;

a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and

an analog holdover circuit for generating an input to said integrator when said phase detector stops receiving the reference clock signal.

2. The phase locked loop of claim 1 further comprising a reference fall detector circuit that is operative to detect when said phase detector is no longer receiving the reference clock signal.

3. The phase locked loop of claim 2 further comprising a switch that is operable to couple either the phase detector output or the output from the analog holdover circuit to said integrator in response to a signal from the reference fall detector.

4. The phase locked loop of claim 3 wherein said switch comprises a pair of data selectors.

5. The phase locked loop of claim 1 wherein said analog holdover circuit comprises a comparator and a DC voltage generating circuit, said comparator having a first input that is coupled to the output of said integrator and a second input that is coupled to the output of said DC voltage generating circuit, said DC voltage generating circuit being controllable to generate one of a plurality of DC voltage levels.

6. The phase locked loop of claim 5 wherein said analog holdover circuit further comprises a digital gain attenuator chopper that is operative to reduce the gain of a loop comprising said comparator and said integrator, said digital gain attenuator chopper having an input that is coupled to the output of said comparator and an output that is coupled to said integrator through a switch.

7. The phase locked loop of claim 6 wherein said digital gain attenuator comprises a pulse width modulator circuit and a pair of AND gates.

8. The phase locked loop of claim 5 wherein said DC voltage generating circuit comprises a pulse width modulator coupled to a low pass filter.

9. The phase locked loop of claim 5 wherein said analog holdover circuit further comprises a controller that is coupled to said comparator and said DC voltage generating circuit, said controller being operative to monitor the output of said comparator, said controller also being operative to adjust the DC voltage output from said DC voltage generating circuit.

10. The phase locked loop of claim 9 wherein said controller is operative to store a setting that causes ad DC voltage generating circuit to generate a voltage approximately equal to the voltage output from said integrator when the reference clock signal is present at the phase detector.

11. An improved phase locked loop having a phase detector for comparing a reference signal with a feedback signal and for generating phase pulses having a pulse width corresponding to the phase difference between the reference signal and the feedback signal, an integrator coupled to the phase pulses for generating a voltage level corresponding to the pulse width of the phase pulses, and a voltage controlled oscillator coupled to the voltage level for generating the feedback signal, the improvement comprising:

an analog holdover circuit for generating an input to the integrator when the phase detector stops receiving a reference clock signal.

12. The improved phase locked loop of claim 11 wherein said analog holdover circuit comprises a comparator and a DC voltage generating circuit, the comparative having a first input that is coupled to the output of said integrator and a second input that is coupled to the output of said DC voltage generating circuit, said DC voltage generating circuit being controllable to generate one of a plurality of DC voltage levels.

13. The improved phase locked loop of claim 12 wherein said analog holdover circuit further comprises a digital gain attenuator chopper that is operative to reduce the gain of a loop comprising said comparator and said integrator, said digital gain attenuator having an input that is coupled to the output of said comparator and an output that is coupled to said integrator through a switch.

14. The improved phase locked loop of claim 13 wherein said digital gain attenuator comprises a pulse width modulator circuit and a pair of AND gates.

15. The improved phase locked loop of claim 12 wherein said DC voltage generating circuit comprises a pulse width modulator coupled to a low pass filter.

16. The improved phase locked loop of claim 12 wherein said analog holdover circuit further comprises a controller that is coupled to said comparator and said DC voltage generating circuit, said controller being operative to monitor the output of said comparator, said controller also being operative to adjust the DC voltage output from said DC voltage generating circuit.

17. The phase locked loop of claim 16 wherein said controller is operative to store a setting that causes said DC voltage generating circuit to generate a voltage approximately equal to the voltage output from said integrator when the reference clock signal is present at the phase detector.

18. A phase locked loop, comprising:

means for detecting the phase difference between a reference clock signal and a feedback signal;

means for generating a phase voltage corresponding to the phase difference between the reference clock signal and the feedback signal;

means for generating the feedback signal, wherein the feedback signal is characterized by a frequency that varies in proportion to the phase voltage; and

means for generating an input to the integrator when the phase detector stops receiving a reference clock signal.

19. The phase locked loop of claim 18, wherein the means for detecting is a phase detector.

20. The phase locked loop of claim 19, wherein the phase detector generates a positive phase output and a negative phase output.

21. The phase locked loop of claim 20, wherein the phase detector outputs a pulse on the positive or negative phase outputs in proportion to the phase difference between the reference clock signal and the feedback signal.

22. The phase locked loop of claim 21, wherein the means for generating a voltage includes an operational amplifier configured as an integrator.

23. The phase locked loop of claim 18, wherein the means for generating the feedback signal includes a voltage controlled oscillator.

24. The phase locked loop of claim 23, wherein the means for generating the feedback signal further includes a divider circuit coupled to the output of the voltage controlled oscillator for generating the feedback signal by dividing down the frequency of a signal output from the voltage controlled oscillator.

25. The phase locked loop of claim 18 wherein the means for generating an input comprises an analog holdover circuit comprising a comparator and a DC voltage generator circuit.

26. An improved phase locked loop having a phase detector, a voltage controlled oscillator, and an integrator coupled between the phase detector and the voltage controlled oscillator, wherein the integrator includes a positive input and a negative input, the improvement comprising:

an analog holdover circuit coupled to at least one of the positive or the negative inputs of the integrator, said analog holdover circuit being operative to generate an input to the integrator when the phase detector stops receiving a reference clock signal.

27. The improved phase locked loop of claim 26, wherein said analog holdover circuit is coupled to both the positive and negative inputs of the integrator.

28. The improved phase locked loop of claim 27, wherein said analog holdover circuit comprises a comparator and a DC voltage generating circuit, the comparator having a first input that is coupled to the output of said integrator and a second input that is coupled to the output of said DC voltage generating circuit, said DC voltage generating circuit being controllable to generate one of a plurality of DC voltage levels.

29. The improved phase locked loop of claim 28 wherein said analog holdover circuit further comprises a digital gain attenuator chopper that is operative to reduce the gain of a loop comprising said comparator and said integrator, said digital gain attenuator chopper having an input that is coupled to the output of said comparator and an output that is coupled to said integrator through a switch.

30. The improved phase locked loop of claim 29 wherein said digital gain attenuator comprises a pulse width modulator circuit and a pair of AND gates.

31. The improved phase locked loop of claim 28 wherein said DC voltage generating circuit comprises a pulse width modulator coupled to a low pass filter.

32. The improved phase locked loop of claim 28 wherein said analog holdover circuit further comprises a controller that is coupled to said comparator and said DC voltage generating circuit, said controller being operative to monitor the output of said comparator, said controller also being operative to adjust the DC voltage output from said DC voltage generating circuit.

33. The improved phase locked loop of claim 32 wherein said controller is operative to store a setting that causes said DC voltage generating circuit to generate a voltage approximately equal to the voltage output from said integrator when the reference clock signal is present at the phase detector.

34. A method of controlling a phase locked loop having a phase detector, a voltage controlled oscillator, and an integrator coupled between the phase detector and the voltage controlled oscillator, comprising the steps of:

storing the voltage output level from the integrator when there is a reference signal input present at the phase detector;

detecting a reference signal failure; and

generating a driving signal for the integrator when said reference signal failure is detected, said driving signal being operative to drive the integrator to output a voltage level that is equivalent to the stored voltage level.

35. The method of claim 34 wherein said generating step comprises the steps of:

generating a DC voltage level based on the stored voltage level;

comparing the generated DC voltage level to the stored voltage level; and

coupling the output of the comparison to the integrator.

36. The method of claim 35 wherein said coupling step comprises the steps of:

coupling a digital gain attenuator chopper between the comparison output and the integrator to reduce the loop gain.