Comparator-amplifier configuration in an ADC

• US 6,313,779 B1
• Filed: 08/11/2000
• Issued: 11/06/2001
• Est. Priority Date: 06/19/2000
• Status: Expired due to Term

• Current Assignee: Silicon Labs CP, Inc. (Silicon Laboratories Incorporated)
• Original Assignee: Douglas S. Piasecki, Ka Y. Leung
• Inventors: Leung, Ka Y., Piasecki, Douglas S.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US09/637,493
• Time in Patent Office: 452 Days
• Field of Search: 341/155, 341/139, 341/118, 341/150, 341/172, 341/161
• US Class Current: 341/155
• CPC Class Codes: H03M 1/129 Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling H03M1/18 takes precedence; Out-of-range indication
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter

Abstract

An analog-to-digital converter amplifier that is configurable with one gain for driving one terminal of a sampling capacitor while the other terminal is sampled to an analog input signal during one time period, and configurable with a different gain for comparing the analog sample with a DAC-generated reference voltage during a second time period.

Claims

1. A comparator/amplifier configuration for an analog-to-digital converter (ADC) operating in a sample mode and a conversion mode, comprising:

a sample capacitor having a first terminal connected to receive at least one analog sample in the sample mode;

a high open loop gain operational amplifier to which a second terminal of said sample capacitor is connected, said operational amplifier configured in the sample mode for operating with a first low gain, substantially lower than said high open loop gain, to drive the second terminal of said sample capacitor to a reference voltage;

a voltage shifter for shifting the voltage on the first terminal of said sample capacitor to the second terminal thereof during said conversion mode and after the sample mode; and

said operational amplifier being reconfigured in the conversion mode to operate at a second gain which is greater than said first low gain and substantially lower than said high open loop gain. for comparing said analog sample amplitude with a reference voltage to determine a relative magnitude thereof.

2. The comparator/amplifier configuration of claim 1, wherein said amplifier is configured to operate as a moderate gain comparator to thereby increase an operational speed thereof.

3. The comparator/amplifier configuration of claim 1, further including a feedback switch coupled between an input and output of said operational amplifier for providing unity gain thereto.

4. The comparator/amplifier configuration of claim 3, wherein said feedback switch is coupled between an inverting input and a non-inverting output of said operational amplifier.

5. The comparator/amplifier configuration of claim 3, further including a switch control for closing said feedback switch for amplifying said analog sample amplitude before said comparison is carried out.

6. The comparator/amplifier configuration of claim 3 wherein said switch is effective to couple an amplifier offset voltage to the input of said operational amplifier.

7. The comparator/amplifier configuration of claim 1, wherein an open loop gain of said operational amplifier is at least 10,000.

8. The comparator/amplifier configuration of claim 1, further including a gain-setting resistive circuit coupled to said operational amplifier for changing the gain thereof to said second high gain.

9. The comparator/amplifier configuration of claim 8, wherein said gain-setting circuit is coupled between in inverting output and a non-inverting output of said operational amplifier.

10. The comparator/amplifier configuration of claim 8, wherein said gain-setting resistive circuit is coupled to a switch for coupling said gain-setting resistive circuit in and out of said operational amplifier.

11. The comparator/amplifier configuration of claim 8, wherein said gain-setting resistive circuit defines a first gain-setting resistive circuit, and further including a second gain-setting resistive circuit connected in parallel with said first gain-setting resistive circuit, said second gain-setting resistive circuit defining a high gain for said operational amplifier and said first gain-setting resistive circuit defining a low gain for said comparator when switched into operation.

12. The comparator/amplifier configuration of claim 1, wherein said operational amplifier includes differential inputs and differential outputs.

13. The comparator/amplifier configuration of claim 12, wherein said operational amplifier is configured to provide a common mode voltage from an output thereof to a non-inverting input.

14. The comparator/amplifier configuration of claim 13, further including a switch coupled between an inverting output and a common mode output and a non-inverting input of said operational amplifier.

15. The comparator/amplifier configuration of claim 1, further including a secondary amplifier coupled to an output of said operational amplifier for providing additional gain.

16. The comparator/amplifier configuration of claim 15, wherein a gain of said secondary amplifier is about six.

17. The comparator/amplifier configuration of claim 16, further including a third amplifier coupled to an output of said secondary amplifier for providing additional gain.

18. The comparator/amplifier configuration of claim 17, wherein said third amplifier has a gain of about six.

19. The comparator/amplifier configuration of claim 1, further including a plurality of low-gain amplifiers cascaded to amplify the output signals of the operational amplifier with a high speed.

20. A comparator/amplifier configuration for an analog-to-digital converter (ADC), comprising:

a differential input operational amplifier having a high open loop gain for converting an input analog sample amplitude to a digital signal as a function of a reference voltage;

a feedback network coupled between an input and an output of said operational amplifier; and

a switch arrangement coupled to said feedback network for configuring said operational amplifier for low gain when amplifying said input analog sample amplitude, and for configuring said operational amplifier for a higher gain when operating as a comparator in comparing said input analog sample with said reference voltage.

21. The comparator/amplifier configuration of claim 20, wherein said operational amplifier produces an output digital signal when configured as a comparator.

22. The comparator/amplifier configuration of claim 21, further including a plurality of low gain cascaded amplifiers for amplifying at a high speed said output digital signal.

23. The comparator/amplifier configuration of claim 22, wherein a gain of each said cascaded amplifier is about six.

24. The comparator/amplifier configuration of claim 20, wherein said operational amplifier includes differential inputs and differential outputs and said feedback network includes a switched resistive circuit coupled between the differential outputs.

25. The comparator/amplifier configuration of claim 24, further including a switch coupled between an inverting input and a non-inverting output of said differential amplifier for providing a unity gain.

26. The comparator/amplifier configuration of claim 24, wherein said switched resistive circuit causes said operational amplifier to have an open loop gain of about 10,000 when configured as an amplifier, and a gain of about 10 when configured as a comparator.

27. A method of converting analog sample amplitudes with a comparator/amplifier in an analog-to-digital converter, comprising the steps of:

amplifying analog sample amplitudes with a first gain during a first time period;

comparing said analog sample amplitudes during a second time period with a reference voltage at a second gain that is higher than said first gain to thereby produce a logic signal;

in response to said logic signal, generating by a SAR a digital word; and

in response to said digital word, generating by a DAC said reference voltage.

28. The method of claim 27, further including changing the gain by which said analog sample amplitudes are amplified by using an operational amplifier and utilizing different feedback resistors during said different time periods.

29. The method of claim 27, further including using an operational amplifier having differential inputs and differential outputs, and with a high open loop gain, and with a switch coupled between an inverting input and a non-inverting output for providing unity gain during said first time period.

30. The method of claim 27, further including amplifying said digital signal using a plurality of amplifiers cascaded together.

31. The method of claim 30, further including configuring the cascaded amplifiers to each have a low gain to thereby enhance a speed by which the digital signal is processed.