Joint tracking of the carrier phases of the signals received from different satellites

• US 6,313,789 B1
• Filed: 06/10/1999
• Issued: 11/06/2001
• Est. Priority Date: 06/10/1998
• Status: Expired due to Term

• Current Assignee: Topcon GPS, LLC
• Original Assignee: Topcon Positioning Systems Incorporated (Topcon Corporation)
• Inventors: Zhodzishsky, Mark, Ashjaee, Javad
• Primary Examiner(s): Pihulic, Daniel T.
• Application Number:
  US09/330,221
• Time in Patent Office: 880 Days
• Field of Search: 342/357.12, 342/357.02, 342/357.03, 375/343
• US Class Current: 342/357.68
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

Disclosed are methods for increasing the fail-safety characteristics of tracking systems for navigation receivers which receive signals from many satellites. In an exemplary embodiment of the present invention, an individual PLL circuit is used to track the phase of each satellite'"'"'s carrier signal, and a vector common tracking loop is used to track the disturbances of the carrier phases which are caused by one or more common sources, such as the movement of the receiver'"'"'s antenna(s) and/or the phase fluctuation of the receiver'"'"'s main reference oscillator. The vector common tracking loop uses phase information from all of the satellites being tracked, and for this reason can be made more wide-band than each of the individual PLL circuits. The wider bandwidth of the vector common tracking loop provides higher dynamic properties and more safe tracking when faint and weakening satellite signals are present. In another embodiment of the invention, the receiver receives the satellite signals from M≧3 antennas mounted on a common object, and three common tracking loops are added to track the object'"'"'s rotation about its three rotational axes. The common object may comprise any structure, rigid member, or vehicle, such as for example: a platform, pole, aircraft, ship, boat, car, truck, train car, etc. With N satellites being tracked with M antennas, this embodiment performs the joint tracking of up to N×M signals, which increases tracking reliability. The present invention may be used in digital receivers of GPS and GLONASS(GLN) systems where the receiver receives a large number of such signals from many satellites and processes them in order to receive information about the current time and the location and movement of the receiver.

Claims

1. A method of tracking a plurality N (N≧

3) of global positioning satellite signals received by an antenna, each satellite signal having a carrier signal, said method comprising the steps of;

(a) tracking the carrier signal of each of the satellite signals with an individual phase-lock loop (PLL) circuit having a corresponding reference carrier generator which generates a corresponding reference carrier signal, said reference carrier signal having a phase which is approximately equal to the phase of the satellite carrier signal as provided to the PLL circuit, each PLL circuit generating a phase output signal representative of the phase difference between the satellite carrier signal being tracked and the corresponding reference carrier signal;

(b) detecting a change in the position of the antenna within a selected coordinate system from the phase output signals of the individual PLL circuits;

(c) generating a correction signal (W_K) for each individual PLL circuit in relation to the detected change in the antenna'"'"'s position; and

(d) modifying the operation of each individual PLL circuit based on the value of the corresponding correction signal for it.

2. The method of claim 1 wherein each satellite signal further comprises a repeating pseudo-random code signal which is modulated onto its carrier signal, and wherein said method further comprises the steps of:

(e) tracking the pseudo-random signal of each satellite signal with a respective reference code signal in an individual delay-lock loop (DLL) circuit, each satellite signal thereby being tracked by a PLL circuit and a corresponding DLL circuit;

(f) generating a correction signal for an individual DLL circuit from the correction signal (W_K) generated for the corresponding PLL circuit; and

(g) modifying the phase of the reference code signal of said individual DLL circuit based on the value of the correction signal generated by step (f).

3. The method of claim 1 wherein there are a plurality of pseudo-ranges corresponding to the number of satellite carrier signals being tracked by the PLL circuits, each pseudo-range being between the satellite which transmits the satellite carrier signal and the antenna;

and

wherein said step (b) comprises the steps of;

(e) grouping the phase output signals of said PLL circuits in the form of a first vector E_P of signals; and

(f) generating a second vector V_C of signals representative of the matrix multiplication of a geometric pseudo-inverse matrix G with said first vector E_P of signals, said matrix G comprising a pseudo-inverse matrix of a geometric Jacobian matrix H for said plurality of pseudo-ranges or a pseudo-inverse of a complemented geometric Jacobian matrix H₁ for said plurality of pseudo-ranges, the matrix elements of said matrix H or said matrix H₁ being representative of the changes in the pseudo-ranges that would be caused by changes in the antenna'"'"'s position in the selected coordinate system, said second vector V_C of signals being representative of a change in the position of the antenna.

4. The method of claim 3 wherein said step (c) comprises the steps of:

(g) generating a third vector U_C of control signals from said second vector V_C of signals, each signal of said third vector U_C being generated by filtering a corresponding signal of said second vector V_C;

(h) generating a fourth vector W of signals representative of the matrix multiplication of a geometric Jacobian matrix H with the third vector U_C of control signals, each said signal of said fourth vector W being one of said correction signals (W_K) for a respective PLL circuit.

5. The method of claim 4 wherein each individual PLL circuit further comprises a loop filter which has an input and which generates a PLL loop control signal (U_k) in response to a signal coupled to the loop filter'"'"'s input, the signal coupled to the input of the loop filter being representative of the phase difference between the satellite carrier signal being tracked by the PLL circuit and the corresponding reference carrier signal of the PLL circuit;

wherein said step (a) comprises the step of varying the output phase of the reference carrier generator of each PLL circuit in response to its PLL loop control signal (U_k); and

wherein said step (d) comprises the step of further varying the output phase of the reference carrier generator of each PLL circuit in response to the corresponding correction signal (W_k) for the PLL circuit.

6. The method of claim 5 wherein the reference carrier generator of each said PLL circuit comprises an input for receiving a control signal, and wherein said generator varies the phase of its output signal in response to the signal at its input, and

wherein said step (d) further comprises the step of combining the corresponding correction signal (W_k) for each PLL circuit with the PLL loop control signal (U_k) of the PLL circuit to generate a combined control signal (U_T,K), and the step of providing said combined control signal to the input of the reference carrier generator of the PLL circuit.

7. The method of claim 4 further comprising the step of removing the phase output signal of a selected PLL circuit from the processing provided in steps (e)-(h), said removal step comprising the steps of:

removing the phase output signal of the selected PLL circuit from said first vector E_P of signals;

forming a reduced matrix H or a reduced matrix H₁ which has the matrix row corresponding to the phase output signal of said selected PLL circuit removed; and

computing a replacement matrix G from said reduced matrix H or from said reduced matrix H₁.

8. The method of claim 7 wherein updated matrix elements of matrices H and G are provided at selected time points, and wherein said step of removing the phase output signal of a selected PLL circuit occurs between said selected time points.

9. The method of claim 5 further comprising the step of removing the phase output signal of a selected PLL circuit from the processing provided in steps(e)-(h), said removal step comprising the steps of:

removing the phase output signal of the selected PLL circuit from said first vector E_P of signals;

forming a reduced matrix H or a reduced matrix H₁ which has the matrix row corresponding to the phase output signal of said selected PLL circuit removed; and

computing a replacement matrix G from said reduced matrix H or from said reduced matrix H₁.

10. The method of claim 9 wherein updated matrix elements of matrices H and G are provided at selected time points, and wherein said step of removing the phase output signal of a selected PLL circuit occurs between said selected time points.

11. The method of claim 9 further comprising the step of decoupling the signal going to the input of the PLL loop filter of said selected PLL circuit.

12. The method of claim 11 further comprising the step of re-introducing the phase output signal of said selected PLL circuit to the processing provided in steps (e)-(h), said re-introduction step comprising the steps of:

forming an augmented matrix H or an augmented matrix H₁ which includes a matrix row corresponding to said selected PLL circuit; and

thereafter computing a replacement matrix G from said augmented matrix H or augmented matrix H₁;

thereafter providing the phase output signal of said selected PLL circuit to said first vector E_P of signals;

thereafter waiting a period of time; and

thereafter re-coupling the signal to the input of the PLL loop filter of the selected PLL circuit.

13. The method of claim 9 wherein the phase output signal of said selected PLL circuit is removed from said first vector E_P of signals when the signal-to-noise ratio of the satellite signal being tracked by said selected circuit falls below a selected level.

14. The method of claim 9 wherein the phase output signal of said selected PLL circuit is removed from said first vector E_P of signals when the magnitude of the phase output signal of said selected PLL circuit rises above a selected level.

15. The method of claim 9 wherein each said reference carrier signal is in quadrature format having an in-phase component and a quadrature-phase component;

wherein said step (a) comprises the step of generating a first correlation signal (I_K) in said selected PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by said selected PLL circuit by the in-phase component of the reference carrier signal of said selected PLL circuit;

wherein said step (a) further comprises the step of generating a second correlation signal (Q_K) in said selected PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by said selected PLL circuit by the quadrature component of the reference carrier signal of said selected PLL circuit;

wherein said step (a) further comprises the step of generating a quality signal S_K in a form which is a function of the quantity (I_K²+Q_K²); and

wherein the phase output signal of said selected PLL circuit is removed from said first vector E_P of signals when the value of signal S_K falls below a selected level.

16. The method of claim 9 wherein each said reference carrier signal is in quadrature format having an in-phase component and a quadrature-phase component;

wherein said step (a) comprises the step of generating a first correlation signal (I_K) in said selected PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by said selected PLL circuit by the in-phase component of the reference carrier signal of said selected PLL circuit;

wherein said step (a) further comprises the step of generating a second correlation signal (Q_K) in said selected PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by said selected PLL circuit by the quadrature component of the reference carrier signal of said selected PLL circuit;

wherein said step (a) further comprises the step of generating a quality signal S_K in a form which is a function of the quantity (I_K²−

Q_K²); and

wherein the phase output signal of said selected PLL circuit is removed from said first vector E_P of signals when the value of signal S_K falls below a selected level.

17. The method of claim 9 wherein each said reference carrier signal is in quadrature format having an in-phase component and a quadrature-phase component;

wherein said step (a) comprises the step of generating a first correlation signal (I_K) in said selected PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by said selected PLL circuit by the in-phase component of the reference carrier signal of said selected PLL circuit;

wherein said step (a) further comprises the step of generating a second correlation signal (Q_K) in said selected PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by said selected PLL circuit by the quadrature component of the reference carrier signal of said selected PLL circuit;

wherein said step (a) further comprises the step of generating a quality signal S_K in a form which is a function of the quantity arctan(Q_K/I_K); and

wherein the phase output signal of said selected PLL circuit is removed from said first vector E_P of signals when the magnitude of signal S_K rises above a selected level.

18. The method of claim 5 wherein step (d) further comprises the step of further varying the output phase of the reference carrier generator of a selected PLL circuit in response to a signal reflective of the frequency Doppler-shift of the satellite signal being tracked by said selected PLL circuit.

19. The method of claim 4 wherein said step (g) comprises the step of filtering each signal of said second vector V_C of signals with a filter structure which is equivalent to three parallel signal processing paths which receive the signal to be filtered and separately process the signal, the outputs of said paths being combined to provide the filtered output, said first path multiplying the signal by a first gain factor (K₁), said second path multiplying the signal by a second gain factor (K₂) and integrating the signal with one integrator, and said third path multiplying the signal by a third gain factor (K₃) and integrating the signal with two integrators.

20. The method of claim 5 wherein each individual PLL circuit further comprises a correlator which generates a correlation signal from the satellite carrier signal tracked by the PLL circuit and from the reference carrier signal of the PLL circuit, and a phase discriminator which generates an output signal in response to said correlation signal, the output signal of the phase discriminator being provided to the input of the loop filter and being representative of the phase difference between the satellite carrier signal being tracked by the PLL circuit and the corresponding reference carrier signal of the PLL circuit;

wherein the correlator, the phase discriminator, the loop filter, and the reference signal generator of each said PLL circuit collectively comprise a second-order feedback loop whose frequency response has a first bandwidth;

wherein processing steps included by steps (b)-(h) form a common vector tracking loop which conveys a vector feedback signal for each PLL circuit through the processing steps included by steps (b)-(h) and through the reference generator, correlator, and phase discriminator of the PLL circuit;

wherein the frequency response of the common vector tracking loop to changes in at least one of the coordinates of the antenna'"'"'s position has a second bandwidth; and

wherein said second bandwidth is greater than said first bandwidth.

21. The method of claim 20 wherein said step (g) comprises the step of filtering each signal of said second vector V_C of signals with a filter structure which is equivalent to three parallel signal processing paths which receive the signal to be filtered and separately process the signal, the outputs of said paths being combined to provide the filtered output, said first path multiplying the signal by a first gain factor (K₁), said second path multiplying the signal by a second gain factor (K₂) and integrating the signal with one integrator, and said third path multiplying the signal by a third gain factor (K₃) and integrating the signal with two integrators.

22. The method of claim 20 wherein the said second bandwidth is greater than said first bandwidth by a factor which is between approximately 4 and approximately 20.

23. The method of claim 22 wherein said first bandwidth is between approximately 1 Hz and approximately 5 Hz.

24. The method of claim 23 wherein the loop control signals (U_k) of the individual PLL circuits are generated in digital form and the values thereof are provided a first number of times per second, said first number being between approximately 10 and approximately 200;

and

wherein the phase output signal of the individual PLL circuits, the signals vector V_C, the signals of vector U_C, and the signals of vector W are generated in digital form and the values thereof are provided a second number of times per second, said second number being between approximately 200 and approximately 1,000.

25. The method of claim 20 wherein each said reference carrier signal is in quadrature format having an in-phase component and a quadrature-phase component;

wherein said step (a) comprises the step of generating a first correlation signal (I_K) in each PLL circuit, said first correlation signal (I_K) being generated in digital form and the values thereof are provided a first number of times per second, said step including the step of multiplying the satellite carrier signal being tracked by the PLL circuit by the in-phase component of the reference carrier signal of the PLL circuit, wherein there are N said first correlation signals (K=1 to K=N);

wherein said step (a) further comprises the step of generating a second correlation signal (Q_K) in each PLL circuit, said second correlation signal (Q_K) being generated in digital form and the values thereof are provided a second number of times per second, said step including the step of multiplying the satellite carrier signal being tracked by the PLL circuit by the quadrature component of the reference carrier signal of the PLL circuit, wherein there are N said second correlation signals (K=1 to K=N);

wherein step (a) further comprises the step of generating the phase output signals of each PLL circuit from the corresponding first and second correlation signals of the PLL circuit; and

wherein the second number is greater than said first number, the values of the second correlation signals thereby being provided more frequently than the values said first correlation signal.

26. The method of claim 25 wherein step (a) further comprises the step of generating the phase output signal of a PLL circuit by the steps of:

forming the reciprocal (1/I_K) of the current value of the first correlation signal (I_K), multiplying said reciprocal by the values of the second correlation signal (Q_K) until the value of said first correlation signal is next updated, and thereafter re-forming said reciprocal with the updated value of the first correlation signal (I_K).

27. The method of claim 1 wherein there are a plurality of pseudo-ranges corresponding to the number of satellite carrier signals being tracked by the PLL circuits, each pseudo-range being between the antenna and the satellite which transmits the satellite carrier signal;

wherein each reference carrier generator generates its output from a main reference oscillator whose frequency may vary in time; and

wherein said step (b) comprises the steps of;

grouping the phase output signals of said PLL circuits in the form of a first vector E_P of signals; and

generating a second vector V_D of signals representative of the matrix multiplication of a geometric pseudo-inverse matrix G with said first vector E_P of signals, said matrix G comprising a pseudo-inverse matrix of a complemented geometric Jacobian matrix H₁ for said plurality of pseudo-ranges, the matrix elements of said matrix H₁ being representative of the changes in the pseudo-ranges that would be caused by changes in the antenna'"'"'s position in the selected coordinate system and changes in the oscillation frequency of the main reference oscillator, said second vector V_D of signals having a sub-vector V_C of signals representative of a change in the position of the antenna and a signal Φ

_q representative of a change in the frequency of the main reference oscillator.

28. The method of claim 27 wherein said step (c) comprises the steps of:

generating a third vector U_C of control signals from the sub-vector V_C of said second vector V_D of signals, each signal of said third vector U_C being generated by filtering the corresponding signal of the sub-vector V_C of said second vector V_D of signals;

generating a fourth vector W of signals representative of the matrix multiplication of a geometric Jacobian matrix H with the third vector U_C of signals, the matrix elements of said matrix H being representative of the changes in the pseudo-ranges that would be caused by changes in the antenna'"'"'s position in the selected coordinate system, each said signal of said fourth vector W being one of said correction signals (W_K) for a respective PLL circuit; and

generating a phase correction signal U_q by filtering the signal Φ

_q of the second vector V_D of signals.

29. The method of claim 28 wherein each individual PLL circuit further comprises a loop filter which has an input and which generates a PLL loop control signal (U_k) in response to a signal coupled to the loop filter'"'"'s input, the signal coupled to the input of the loop filter being representative of the phase difference between the satellite carrier signal being tracked by the PLL circuit and the corresponding reference carrier signal of the PLL circuit;

wherein said step (a) comprises the step of varying the output phase of the reference carrier generator of each PLL circuit in response to its PLL loop control signal (U_k); and

wherein said step (d) comprises the step of further varying the output phase of the reference carrier generator of each PLL circuit in response to the corresponding correction signal (W_k) for the PLL circuit.

30. The method of claim 29 wherein the reference carrier generator of each said PLL circuit comprises an input for receiving a control signal, and wherein said generator varies the phase of its output signal in response to the signal at its input, and

wherein said step (d) further comprises the step of combining the corresponding correction signal (W_k) for each PLL circuit with the PLL loop control signal (U_k) of the PLL circuit to generate a combined control signal (U_T,K), and the step of providing said combined control signal to the input of the reference carrier generator of the PLL circuit.

31. The method of claim 28 further comprising the step of modifying the phase of the main reference oscillator in response to said phase correction signal U_q.

79. The method of claim 31 further comprising the steps of:

receiving a frequency-shift signal U<sub>Δ

ω</sub>

representative of the frequency shift Δ

ω

of the main reference oscillator relative to the global GPS reference frequency;

accumulating said frequency-shift signal U<sub>Δ

ω</sub>

; and

adding the accumulated frequency-shift signal to said phase correction signal Uq.

32. A method of tracking a plurality N (N≧

3) of global positioning satellite signals received by an antenna, each satellite signal having a carrier signal, said method comprising the steps of;

(a) tracking the carrier signal of each of the satellite signals with an individual phase-lock loop (PLL) circuit having a corresponding reference carrier generator which generates a corresponding reference carrier signal, said reference carrier signal having a phase which is approximately equal to the phase of the satellite carrier signal as provided to the PLL circuit, each PLL circuit generating a phase output signal representative of the phase difference between the satellite carrier signal being tracked and the corresponding reference carrier signal, each reference carrier generator generating its output from a main reference oscillator whose frequency may vary in time;

(b) detecting a change in the frequency of the main reference oscillator during an interval of time from the phase output signals of the individual PLL circuits;

(c) generating a phase correction signal U_q in response to the detected change; and

(d) modifying the operation of at least one individual PLL circuit based on the value of said phase correction signal U_q.

33. The method of claim 32 wherein each said reference carrier signal is in quadrature format having an in-phase component and a quadrature-phase component;

wherein said step (a) comprises the step of generating a first correlation signal (I_K) in each PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by the PLL circuit by the in-phase component of the reference carrier signal of the PLL circuit, wherein there are N said first correlation signals (K=1 to K=N);

wherein said step (a) further comprises the step of generating a second correlation signal (Q_K) in each PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by the PLL circuit by the quadrature component of the reference carrier signal of the PLL circuit, wherein there are N said second correlation signals (K=1 to K=N), the phase output signal of a PLL circuit comprising the second correlation signal of the PLL circuit; and

wherein step (b) comprises the step of generating a plurality of product signals, each product signal being proportional to the multiplication product of the first and second correlation signals (I_K, Q_K) of a PLL circuit, and the step of generating a common phase signal Φ

_q from a summation of said product signals.

34. The method of claim 33 wherein said step (c) comprises the step of filtering said phase signal Φ

_q and generating said phase correction signal U_q in relation to the filtered phase signal Φ

_q.

35. The method of claim 33 wherein step (b) further comprises the step of forming a normalization signal related to the magnitudes of a plurality of said first correction signals (I_K), and the step of scaling said phase signal Φ

_q by said normalization signal.

36. The method of claim 35 wherein said phase signal Φ

_q is generated in the form;

${\mathrm{\Phi <br><br>}}_q=\left(\frac{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>Q_K*I_K}{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>I_K^2}\right).$

37. The method of claim 35 wherein said phase signal Φ

_q is generated in the form;

${\mathrm{\Phi <br><br>}}_q=\left(\frac{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>Q_K*I_K}{{\left(\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br><br><br>\text{\hspace{1em}<br><br>}<br><br>I_K<br><br>\right)}^2}\right).$

38. The method of claim 35 wherein said phase signal Φ

_q is generated in the form;

${\mathrm{\Phi <br><br>}}_q=\arctan <br><br>\left(\frac{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>Q_K*I_K}{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>I_K^2}\right).$

39. The method of claim 35 wherein said phase signal Φ

_q is generated in the form;

${\mathrm{\Phi <br><br>}}_q=\mathrm{ODD}<br><br>\left(\frac{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>Q_K*I_K}{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>I_K^2}\right),$

where ODD(*) is an odd function.

40. The method of claim 35 wherein said phase signal Φ

_q is generated in the form;

${\mathrm{\Phi <br><br>}}_q=\mathrm{ODD}<br><br>\left(\frac{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>Q_K*I_K}{{\left(\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br><br><br>I_K<br><br>\right)}^2}\right),$

where ODD(*) is an odd function.

41. The method of claim 33 wherein each said first correlation signal (I_K) is generated in digital form and the value thereof is provided a first number p of times per second;

wherein each said second correlation signal (Q_K) is generated in digital form and the value thereof is provided a second number q of times per second where q is greater than p.

42. The method of claim 41 wherein the value of said first correlation signal (I_K) is provided at periodic intervals having a first period T_L, and wherein the value of said second correlation signal (Q_K) is provided at periodic intervals having a second period T_f.

43. The method of claim 32 wherein each said individual phase-lock loop circuit modified by said step (d) comprises a phase discriminator which generates an output signal representative of the phase difference between the satellite carrier signal being tracked and the circuit'"'"'s reference carrier signal, and a loop filter which generates a PLL loop control signal (U_k) in response to the output signal of said phase discriminator,

wherein said step (a) comprises the step of varying the output phase of the reference carrier generator of each said PLL circuit in response to its PLL loop control signal (U_k);

and

wherein said step (d) comprises the step of further varying the output phase of the reference carrier generator of each said PLL circuit in response to said phase correction signal (U_q).

44. The method of claim 32 further comprising the step of modifying the output frequency of the main reference oscillator in response to said phase correction signal U_q.

45. The method of claim 34 wherein each individual PLL circuit further comprises a loop filter which has an input and which generates a PLL loop control signal (U_k) in response to a signal coupled to the loop filter'"'"'s input, the signal coupled to the input of the loop filter being representative of the phase difference between the satellite carrier signal being tracked by the PLL circuit and the corresponding reference carrier signal of the PLL circuit;

wherein said step (a) comprises the step of varying the output phase of the reference carrier generator of each PLL circuit in response to its PLL loop control signal (U_k); and

wherein said step (d) comprises the step of further varying the output phase of the reference carrier generator of each PLL circuit in response to the phase correction signal (U_q).

46. The method of claim 45 wherein the reference carrier generator of each said PLL circuit comprises an input for receiving a control signal, and wherein said generator varies the phase of its output signal in response to the signal at its input, and

wherein said step (d) further comprises the step of combining the phase correction signal (U_q) with the PLL loop control signal (U_k) of the PLL circuit to generate a combined control signal (U_T,K), and the step of providing said combined control signal to the input of the reference carrier generator of the PLL circuit.

47. The method of claim 46 wherein step (d) further comprises the step of further varying the output phase of the reference carrier generator of a selected PLL circuit in response to a signal reflective of the frequency Doppler-shift of the satellite signal being tracked by said selected PLL circuit.

48. The method of claim 34 wherein said step of filtering said phase signal Φ

_q comprises the step of filtering said signal Φ

_q with a filter structure which is equivalent to three parallel signal processing paths which receive the signal to be filtered and separately process the signal, the outputs of said paths being combined to provide the filtered output, said first path multiplying the signal by a first gain factor (K₁), said second path multiplying the signal by a second gain factor (K₂) and integrating the signal with one integrator, and said third path multiplying the signal by a third gain factor (K₃) and integrating the signal with two integrators.

49. The method of claim 45 wherein each individual PLL circuit further comprises a correlator which generates a correlation signal from the satellite carrier signal tracked by the PLL circuit and from the reference carrier signal of the PLL circuit, and a phase discriminator which generates an output signal in response to said correlation signal, the output signal of the phase discriminator being provided to the input of the loop filter and being representative of the phase difference between the satellite carrier signal being tracked by the PLL circuit and the corresponding reference carrier signal of the PLL circuit;

wherein the correlator, the phase discriminator, the loop filter, and the reference signal generator of each said PLL circuit collectively comprise a second-order feedback loop whose frequency response has a first bandwidth;

wherein processing steps included by steps (b)-(d) form a common phase loop which conveys signal Φ

_q as a feedback signal to each PLL;

wherein the frequency response of the common phase loop as seen by each feedback signal has a second bandwidth; and

wherein said second bandwidth is greater than said first bandwidth.

50. The method of claim 49 wherein the said second bandwidth is greater than said first bandwidth by a factor which is between approximately 4 and approximately 20.

51. The method of claim 50 wherein said first bandwidth is between approximately 1 Hz and approximately 5 Hz.

52. The method of claim 51 wherein the phase output signal and the loop control signal (U_k) of each individual PLL circuit, the phase signal Φ

_q, and the phase correction signal U_q are generated in digital form,

wherein the values of the loop control signals (U_k) of the individual PLL circuits are provided a first number of times per second, said first number being between approximately 10 and approximately 200; and

wherein the values of the phase output signals of the individual PLL circuits, the phase signal Φ

_q, and the phase correction signal U_q are provided a second number of times per second, said second number being between approximately 200 and approximately 1,000.

80. The method of claim 32 further comprising the steps of:

receiving a frequency-shift signal U<sub>Δ

ω</sub>

representative of the frequency shift Δ

ω

of the main reference oscillator relative to the global GPS reference frequency;

accumulating said frequency-shift signal U<sub>Δ

ω</sub>

; and

adding the accumulated frequency-shift signal to said phase correction signal Uq.

53. A method of tracking a plurality N (N≧

3) of satellite signals using a plurality M (M≧

2) of antennas and a plurality K of individual phase-lock loop (PLL) circuits, said plurality K being greater than 3 and less than or equal to M*N, said antennas being disposed on an object, said method comprising the steps of;

(a) tracking, in each of said plurality K of PLL circuits, the carrier signal of a satellite signal as received by an antenna, each said PLL circuit having a corresponding reference carrier generator which generates a corresponding reference carrier signal, said reference carrier signal having a phase which is approximately equal to the phase of the satellite carrier signal as provided to the PLL circuit, each PLL circuit generating a phase output signal representative of the phase difference between the carrier signal of the satellite being tracked and the corresponding reference carrier signal, each PLL circuit using the output of one of said antennas;

(b) detecting a change in the position or directional orientation of the object within a selected coordinate system from the phase output signals of the individual PLL circuits;

(c) generating a correction signal (W_K) for each individual PLL circuit in relation to the detected change in the object'"'"'s position and directional orientation; and

(d) modifying the operation of each individual PLL circuit based on the value of the corresponding correction signal for it.

54. The method of claim 53 wherein there are a plurality of pseudo-ranges corresponding to the number of PLL circuits which are tracking satellite carrier signals, each pseudo-range being between a satellite whose carrier signal is being tracked by a corresponding PLL circuit and the antenna being used by the same PLL circuit, and wherein said step (b) comprises the steps of:

(e) grouping the phase output signals of said PLL circuits in the form of a first vector E_P of signals; and

(f) generating a second vector V_C of signals representative of the matrix multiplication of a geometric pseudo-inverse matrix G′

with said first vector E_P of signals, said matrix G′

comprising a pseudo-inverse matrix of a geometric Jacobian matrix H′

for said plurality of pseudo-ranges or a pseudo-inverse of a complemented geometric Jacobian matrix H₁′

for said plurality of pseudo-ranges, the matrix elements of said matrix H′

or said matrix H₁′

being representative of the changes in the pseudo-ranges that would be caused by changes in the position and directional orientation of the object within said selected coordinate system, said second vector V_C of signals being representative of a change in the position and directional orientation of the object.

55. The method of claim 54 wherein said step (c) comprises the steps of:

(g) generating a third vector U_C of control signals from said second vector V_C of signals, each signal of said third vector U_C being generated by filtering the corresponding signal of said second vector V_C;

(h) generating a fourth vector W of signals representative of the matrix multiplication of a geometric Jacobian matrix H′

with the third vector U_C of control signals, the matrix elements of said matrix H′

being representative of the changes in the pseudo-ranges that would be caused by changes in the position and directional orientation of the object within said selected coordinate system, each said signal of said fourth vector W being one of said correction signals (W_K) for a respective PLL circuit.

56. The method of claim 55 wherein each individual PLL circuit further comprises a loop filter which has an input and which generates a PLL loop control signal (U_k) in response to a signal coupled to the loop filter'"'"'s input, the signal coupled to the input of the loop filter being representative of the phase difference between the satellite carrier signal being tracked by the PLL circuit and the corresponding reference carrier signal of the PLL circuit;

wherein said step (a) comprises the step of varying the output phase of the reference carrier generator of each PLL circuit in response to its PLL loop control signal (U_k); and

wherein said step (d) comprises the step of further varying the output phase of the reference carrier generator of each PLL circuit in response to the corresponding correction signal (W_k) for the PLL circuit.

57. The method of claim 56 wherein the reference carrier generator of said each PLL circuit comprises an input for receiving a control signal, and wherein said generator varies the phase of its output signal in response to the signal at its input, and

wherein said step (d) further comprises the step of combining the corresponding correction signal (W_k) for each PLL circuit with the PLL loop control signal (U_k) of the PLL circuit to generate a combined control signal (U_T,K), and the step of providing said combined control signal to the input of the reference carrier generator of the PLL circuit.

58. The method of claim 57 wherein step (d) further comprises the step of further varying the output phase of the reference carrier generator of at least one PLL circuit in response to a signal reflective of the frequency Doppler-shift of the satellite signal being tracked by each said PLL circuit.

59. The method of claim 53 wherein there are a plurality of pseudo-ranges corresponding to the number of PLL circuits which are tracking satellite carrier signals, each pseudo-range being between a satellite whose carrier signal is being tracked by a corresponding PLL circuit and the antenna being used by the same PLL circuit,

wherein each reference carrier generator generates its output from a main reference oscillator whose frequency may vary in time;

and

wherein said step (b) comprises the steps of;

(e) grouping the phase output signals of said PLL circuits in the form of a first vector E_P of signals; and

(f) generating a second vector V_D of signals representative of the matrix multiplication of a geometric pseudo-inverse matrix G′

with said first vector E_P of signals, said matrix G′

comprising a pseudo-inverse matrix of a complemented geometric Jacobian matrix H₁′

for said plurality of pseudo-ranges, the matrix elements of said matrix H₁′

being representative of the changes in the pseudo-ranges that would be caused by changes in the position and directional orientation of the object within said selected coordinate system and by changes in the oscillation frequency of the main reference oscillator, said second vector V_D of signals having a sub-vector V_C of signals representative of a change in the position and directional orientation of the object and a signal Φ

_q representative of a change in the frequency of the main reference oscillator.

60. The method of claim 59 wherein said step (c) comprises the steps of:

(g) generating a third vector U_C of control signals from the sub-vector V_C of said second vector V_D of signals, each signal of said third vector U_C being generated by filtering the corresponding signal of the sub-vector V_C said second vector V_D of signals;

(h) generating a fourth vector W of signals representative of the matrix multiplication of a geometric Jacobian matrix H′

with the third vector U_C of control signals, the matrix elements of said matrix H′

being representative of the changes in the pseudo-ranges that would be caused by changes in the position and directional orientation of the object within said selected coordinate system, each said signal of said fourth vector W being one of said correction signals (W_K) for a respective PLL circuit; and

generating a phase correction signal U_q by filtering the signal Φ

_q of the second vector V_D of signals.

61. The method of claim 60 further comprising the step of modifying the frequency of the main reference oscillator in response to said phase correction signal U_q.

62. The method of claim 60 wherein each individual PLL circuit further comprises a loop filter which has an input and which generates a PLL loop control signal (U_k) in response to a signal coupled to the loop filter'"'"'s input, the signal coupled to the input of the loop filter being representative of the phase difference between the satellite carrier signal being tracked by the PLL circuit and the corresponding reference carrier signal of the PLL circuit;

wherein said step (a) comprises the step of varying the output phase of the reference carrier generator of each PLL circuit in response to its PLL loop control signal (U_k); and

wherein said step (d) comprises the step of further varying the output phase of the reference carrier generator of each PLL circuit in response to the corresponding correction signal (W_k) for the PLL circuit.

63. The method of claim 62 wherein the reference carrier generator of each said PLL circuit comprises an input for receiving a control signal, and wherein said generator varies the phase of its output signal in response to the signal at its input, and

wherein said step (d) further comprises the step of combining the corresponding correction signal (W_k) for each PLL circuit with the PLL loop control signal (U_k) of the PLL circuit to generate a combined control signal (U_T,K), and the step of providing said combined control signal to the input of the reference carrier generator of the PLL circuit.

64. The method of claim 55 further comprising the step of removing the phase output signal of a selected PLL circuit from the processing provided in steps (e)-(h), said removal step comprising the steps of:

removing the phase output signal of the selected PLL circuit from said first vector E_P of signals;

forming a reduced matrix H′

or a reduced matrix H₁′

which has the matrix row corresponding to the phase output signal of said selected PLL circuit removed; and

computing a replacement matrix G′

from said reduced matrix H′

or from said reduced matrix H₁′

.

65. The method of claim 64 wherein updated matrix elements of matrices H′

and G′

are provided at selected time points, and wherein said step of removing the phase output signal of a selected PLL circuit occurs between said selected time points.

66. The method of claim 56 further comprising the step of removing the phase output signal of a selected PLL circuit from the processing provided in steps (e)-(h), said removal step comprising the steps of:

removing the phase output signal of the selected PLL circuit from said first vector E_P of signals;

forming a reduced matrix H′

or a reduced matrix H₁′

which has the matrix row corresponding to the phase output signal of said selected PLL circuit removed; and

computing a replacement matrix G′

from said reduced matrix H′

or from said reduced matrix H₁′

.

67. The method of claim 66 wherein updated matrix elements of matrices H′

and G′

are provided at selected time points, and wherein said step of removing the phase output signal of a selected PLL circuit occurs between said selected time points.

68. The method of claim 66 further comprising the step of decoupling the signal going to the input of the PLL loop filter of the selected PLL circuit.

69. The method of claim 68 further comprising the step of re-introducing the phase output signal of said selected PLL circuit to the processing provided in steps (e)-(h), said re-introduction step comprising the steps of:

forming an augmented matrix H′

or an augmented matrix H₁′

which includes a matrix row corresponding to selected PLL circuit; and

thereafter computing a replacement matrix G′

from said augmented matrix H′

or augmented matrix H₁′

;

thereafter providing the phase output signal of said selected PLL circuit to said first vector E_P of signals;

thereafter waiting a period of time; and

thereafter re-coupling the signal to the input of the PLL loop filter of the selected PLL circuit.

70. The method of claim 66 wherein the phase output signal of said selected PLL circuit is removed from said first vector E_P of signals when the signal-to-noise ratio of the satellite signal being tracked by said selected circuit falls below a selected level.

71. The method of claim 55 wherein said step (g) comprises the step of filtering each signal of said second vector V_C of signals with a filter structure which is equivalent to three parallel signal processing paths which receive the signal to be filtered and separately process the signal, the outputs of said paths being combined to provide the filtered output, said first path multiplying the signal by a first gain factor (K₁), said second path multiplying the signal by a second gain factor (K₂) and integrating the signal with one integrator, and said third path multiplying the signal by a third gain factor (K₃) and integrating the signal with two integrators.

72. The method of claim 56 wherein each individual PLL circuit further comprises a correlator which generates a correlation signal from the satellite carrier signal tracked by the PLL circuit and from the reference carrier signal of the PLL circuit, and a phase discriminator which generates an output signal in response to said correlation signal, the output signal of the phase discriminator being provided to the input of the loop filter and being representative of the phase difference between the satellite carrier signal being tracked by the PLL circuit and the corresponding reference carrier signal of the PLL circuit;

wherein the correlator, the phase discriminator, the loop filter, and the reference signal generator of each said PLL circuit collectively comprise a second-order feedback loop whose frequency response has a first bandwidth;

wherein processing steps included by steps (b)-(h) form a common vector tracking loop which conveys a vector feedback signal for each PLL circuit through the processing steps included by steps (b)-(h) and through the reference generator, correlator, and phase discriminator of the PLL circuit;

wherein the frequency response of the common vector tracking loop to changes in at least one of the coordinates of the antenna'"'"'s position and orientation has a second bandwidth; and

wherein said second bandwidth is greater than said first bandwidth.

73. The method of claim 72 wherein said step (g) comprises the step of filtering each signal of said second vector V_C of signals with a filter structure which is equivalent to three parallel signal processing paths which receive the signal to be filtered and separately process the signal, the outputs of said paths being combined to provide the filtered output, said first path multiplying the signal by a first gain factor (K₁), said second path multiplying the signal by a second gain factor (K₂) and integrating the signal with one integrator, and said third path multiplying the signal by a third gain factor (K₃) and integrating the signal with two integrators.

74. The method of claim 72 wherein the said second bandwidth is greater than said first bandwidth by a factor which is between approximately 4 and approximately 20.

75. The method of claim 74 wherein said first bandwidth is between approximately 1 Hz and approximately 5 Hz.

76. The method of claim 75 wherein the loop control signals (U_k) of the individual PLL circuits are generated in digital form and the values thereof are provided a first number of times per second, said first number being between approximately 10 and approximately 200;

and

wherein the phase output signal of the individual PLL circuits, the signals vector V_C, the signals of vector U_C, and the signals of vector W are generated in digital form and the values thereof are provided a second number of times per second, said second number being between approximately 200 and approximately 1,000.

77. The method of claim 72 wherein each said reference carrier signal is in quadrature format having an in-phase component and a quadrature-phase component;

wherein said step (a) comprises the step of generating a first correlation signal (I_K) in each PLL circuit, said first correlation signal (I_K) being generated in digital form and the values thereof are provided a first number of times per second, said step including the step of multiplying the satellite carrier signal being tracked by the PLL circuit by the in-phase component of the reference carrier signal of the PLL circuit, wherein there are N said first correlation signals (K=1 to K=N);

wherein said step (a) further comprises the step of generating a second correlation signal (Q_K) in each PLL circuit, said second correlation signal (Q_K) being generated in digital form and the values thereof are provided a second number of times per second, said step including the step of multiplying the satellite carrier signal being tracked by the PLL circuit by the quadrature component of the reference carrier signal of the PLL circuit, wherein there are N said second correlation signals (K=1 to K=N);

wherein step (a) further comprises the step of generating the phase output signals of each PLL circuit from the corresponding first and second correlation signals of the PLL circuit; and

wherein the second number is greater than said first number, the values of the second correlation signals thereby being provided more frequently than the values said first correlation signals.

78. The method of claim 77 wherein step (a) further comprises the step of generating the phase output signal of a PLL circuit by the steps of:

forming the reciprocal (1/I_K) of the current value of the first correlation signal (I_K), multiplying said reciprocal by the values of the second correlation signal (Q_K) until the value of said first correlation signal is next updated, and thereafter re-forming said reciprocal with the updated value of the first correlation signal (I_K).

81. A method of tracking a first plurality N (N≧

3) of L1-band global positioning satellite signals received by an antenna from a set of selected satellites, and a second plurality M of L2-band global positioning satellite signals received by the antenna, each satellite signal having a carrier signal, and each L2 band satellite signal and a corresponding one of the L1-band satellite signals being transmitted from a common satellite, said method comprising the steps of;

(a) tracking the carrier signal of each of the L1-band satellite signals with an individual phase-lock loop (PLL) circuit having a corresponding reference carrier generator which generates a corresponding reference carrier signal, said reference carrier signal having a phase which is approximately equal to the phase of the L1-band satellite carrier signal as provided to the PLL circuit, each L1-band PLL circuit generating a phase output signal representative of the phase difference between the L1-band satellite carrier signal being tracked and the corresponding reference carrier signal, each L1-band PLL circuit further having a loop filter which has an input and which generates an L1-band PLL loop control signal U_K,L1 in response to a signal coupled to the loop filter'"'"'s input, the signal coupled to the input of the loop filter being representative of the phase difference between the satellite carrier signal being tracked by the L1-band PLL circuit and the corresponding reference carrier signal of the L1-band PLL circuit;

(b) tracking the carrier signal of each L2-band satellite signal with an individual phase-lock loop circuit having a corresponding reference carrier generator which generates a corresponding reference carrier signal, said reference carrier signal having a phase which is approximately equal to the phase of the L2-band satellite carrier signal as provided to the L2-band PLL circuit, each L2-band PLL circuit generating a phase output signal representative of the phase difference between the L2-band satellite carrier signal being tracked and the corresponding reference carrier signal, each individual L2-band PLL circuit further having a loop filter which has an input and which generates an L2-band PLL loop control signal U_K,L2 in response to a signal coupled to the loop filter'"'"'s input, the signal coupled to the input of the loop filter being representative of the phase difference between the L2-band satellite carrier signal being tracked by the L2-band PLL circuit and the corresponding reference carrier signal of the L2-band PLL circuit, said step (b) comprising the step of varying the output phase of the reference carrier generator of each L2-band PLL circuit in response to the loop control signal U_K,L2 of said L2-band PLL circuit;

(c) generating a correction signal for each L2-band PLL circuit from at least the L1-band PLL loop control signal U_K,L1 of the corresponding L1-band PLL circuit;

(d) further varying the output phase of the reference carrier generator of each L2-band PLL circuit in response to its correction signal;

(e) detecting a common phase shift in the phase output signals of the L2-band PLL circuits;

(f) generating an L2-band phase correction signal Uq_,L2 in response to the detected common phase shift; and

(g) further varying the output phase of the reference carrier generator of at least one L2-band PLL circuit in response to the value of said L2-band phase correction signal Uq_,L2.

82. The method of claim 81 wherein each said reference carrier signal in each L2-band PLL circuit is in quadrature format having an in-phase component and a quadrature-phase component;

wherein said step (b) comprises the step of generating a first correlation signal (I_K) in each L2-band PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by the L2-band PLL circuit by the in-phase component of the reference carrier signal of the L2-band PLL circuit, wherein there are M said first correlation signals (K=1 to K=M);

wherein said step (b) further comprises the step of generating a second correlation signal (Q_K) in each L2-band PLL circuit, said step including the step of multiplying the satellite carrier signal being tracked by the L2-band PLL circuit by the quadrature component of the reference carrier signal of the L2-band PLL circuit, wherein there are M said second correlation signals (K=1 to K=M), the phase output signal of an L2-band PLL circuit comprising the second correlation signal of the L2-band PLL circuit;

wherein step (e) comprises the step of generating a plurality of product signals, each product signal being proportional to the multiplication product of the first and second correlation signals (I_K, Q_K) of an L2-band PLL circuit, and the step of generating a common phase signal Φ

_q,L2 from a summation of said product signals, said phase signal Φ

_q,L2 being representative of the detected common phase shift.

83. The method of claim 82 wherein said phase signal Φ

_q,L2 is generated as a function of at least one of the forms of;

$\left(\frac{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>Q_K*I_K}{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>I_K^2}\right),\left(\frac{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>Q_K*I_K}{{\left(\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br><br><br>I_K<br><br>\right)}^2}\right),\arctan <br><br>\left(\frac{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>Q_K*I_K}{\underset{K=1}{\overset{N}{\sum <br><br>}}<br><br>I_K^2}\right),$

and odd functions thereof.

84. An apparatus for tracking a plurality N of at least three global positioning satellite signals, each satellite signal having a carrier signal, said apparatus comprising:

a first plurality of K tracking channels, each tracking channel tracking a selected one of said N satellite signals, each said tracking channel having a phase-lock loop (PLL) circuit which tracks the phase of the carrier signal of the satellite signal being tracked by said channel, said phase-lock loop (PLL) circuit having a corresponding reference carrier generator which generates a corresponding reference carrier signal, said reference carrier signal having a phase which is approximately equal to the phase of the satellite carrier signal as provided to the PLL circuit, each PLL circuit generating a phase output signal representative of the phase difference between the satellite carrier signal being tracked and the corresponding reference carrier signal;

at least one common tracking loop responsive to the phase output signals of said plurality K of tracking channels which detects changes in the phase output signals which are caused by a common source, each said common tracking loop generating at least one correction signal; and

wherein the operation of at least one PLL circuit is modified in response to said correction signal.

85. The apparatus of claim 84 wherein each reference carrier generator generates its output from a main reference oscillator whose frequency may vary in time;

wherein one of said common tracking loops detects changes in the frequency of said main reference oscillator during an interval of time and generates a phase correction signal U_q in response to the detected change; and

wherein the operation of at least one PLL circuit is modified by varying the output frequency of the main reference oscillator in response to said phase correction signal U_q.

86. The apparatus of claim 84 wherein each reference carrier generator generates its output from a main reference oscillator whose phase and frequency may vary in time;

wherein one of said common tracking loops detects changes in the frequency of said main reference oscillator during an interval of time and generates a phase correction signal U_q in response to the detected change; and

wherein the operation of at least one PLL circuit is modified by varying the output phase of its reference carrier generator in response to its PLL loop control signal (U_k).

87. The apparatus of claim 84 wherein at least two common loops detect changes in the phase output signals which are caused by a change in the position of the antenna within a selected coordinate system, said common loops collectively generating a correction signal (W_K) for at least one individual PLL circuit in relation to the detected change in the antenna'"'"'s position, and

wherein the operation of at least one PLL circuit is modified by varying the output frequency of its reference carrier generator in response to the correction signal (W_K) for the individual PLL circuit.

88. The apparatus of claim 87 wherein there are a plurality of pseudo-ranges corresponding to the number of satellite carrier signals being tracked by the PLL circuits, each pseudo-range being between the satellite which transmits the satellite carrier signal and the antenna;

and wherein said at least two common loops;

group the phase output signals of the PLL circuits in the form of a first vector E_P of signals,

generate a second vector V_C of signals representative of the matrix multiplication of a geometric pseudo-inverse matrix G with said first vector E_P of signals, said matrix G comprising a pseudo-inverse matrix of a geometric Jacobian matrix H for said plurality of pseudo-ranges or a pseudo-inverse of a complemented geometric Jacobian matrix H₁ for said plurality of pseudo-ranges, the matrix elements of said matrix H or said matrix H₁ being representative of the changes in the pseudo-ranges that would be caused by changes in the antenna'"'"'s position in the selected coordinate system, said second vector V_C of signals being representative of a change in the position of the antenna,

generate a third vector U_C of control signals from said second vector V_C of signals, each signal of said third vector U_C being generated by filtering a corresponding signal of said second vector V_C, and

generate a fourth vector W of signals representative of the matrix multiplication of a geometric Jacobian matrix H with the third vector U_C of control signals, each said signal of said fourth vector W being a correction signals (W_K) for a respective PLL circuit.

89. The apparatus of claim 84 wherein said apparatus tracking a plurality N (N≧

3) of satellite signals using a plurality M (M≧

2) of antennas and a plurality K of individual phase-lock loop (PLL) circuits, said plurality K being greater than 3 and less than or equal to M*N, said antennas being disposed on an object;

wherein each of said plurality K of PLL circuits uses the output of one of said antennas and tracks the carrier signal of a satellite signal as received by the antenna;

wherein at least two common loops detect changes in the phase output signals which are caused by a change in the position or directional orientation of the object within a selected coordinate system, said common loops collectively generating a correction signal (W_K) for at least one individual PLL circuit in relation to the detected change;

wherein the operation of at least one PLL circuit is modified by varying the output frequency of its reference carrier generator in response to the correction signal (W_K) for the individual PLL circuit;

wherein there are a plurality of pseudo-ranges corresponding to the number of PLL circuits which are tracking satellite carrier signals, each pseudo-range being between a satellite whose carrier signal is being tracked by a corresponding PLL circuit and the antenna being used by the same PLL circuit; and

wherein said at least two common loops;

group the phase output signals of said PLL circuits in the form of a first vector E_P of signals,

generate a second vector V_C of signals representative of the matrix multiplication of a geometric pseudo-inverse matrix G′

with said first vector E_P of signals, said matrix G′

comprising a pseudo-inverse matrix of a geometric Jacobian matrix H′

for said plurality of pseudo-ranges or a pseudo-inverse of a complemented geometric Jacobian matrix H₁′

for said plurality of pseudo-ranges, the matrix elements of said matrix H′

or said matrix H₁′

being representative of the changes in the pseudo-ranges that would be caused by changes in the position and directional orientation of the object within said selected coordinate system, said second vector V_C of signals being representative of a change in the position and directional orientation of the object,

generating a third vector U_C of control signals from said second vector V_C of signals, each signal of said third vector U_C being generated by filtering the corresponding signal of said second vector V_C, and

generate a fourth vector W of signals representative of the matrix multiplication of a geometric Jacobian matrix H′

with the third vector U_C of control signals, the matrix elements of said matrix H′

being representative of the changes in the pseudo-ranges that would be caused by changes in the position and directional orientation of the object within said selected coordinate system, each said signal of said fourth vector W being a correction signals (W_K) for a respective PLL circuit.

90. The apparatus of claim 84 wherein said plurality N of satellite signals comprise L1-band global positioning satellite signals which are received by an antenna from a set of selected satellites;

wherein said K tracking channels track corresponding ones of the L1-band global positioning satellite signals, wherein the PLL circuit of each tracking channels further has a loop filter which has an input and an output which generates an L1-band PLL loop control signal U_K,L1 in response to a signal coupled to the loop filter'"'"'s input, the signal coupled to the input of the loop filter being representative of the phase difference between the Li-band satellite carrier signal being tracked by the PLL circuit and the corresponding reference carrier signal of the PLL circuit, wherein each said PLL circuit varies the output phase of its reference carrier generator in response to the loop control signal U_K,L1;

wherein said apparatus further receives a number of L2-band global positioning satellite signals transmitted from the set of selected satellites, each said L2-band satellite signal sharing a common satellite with a corresponding one of the L1-band satellite signals;

wherein said apparatus further comprises;

a number M of additional ones of said tracking channels for tracking a corresponding number M of the L2-band global positioning satellite signals, each PLL circuit of said additional tracking channels being referred to as an L2-band PLL circuit, each L2-band PLL circuit having a loop filter which has an input and an output which generates an L2-band PLL loop control signal U_K,L2 in response to a signal coupled to the loop filter'"'"'s input, the signal coupled to the input of the loop filter being representative of the phase difference between the L2-band satellite carrier signal being tracked by the L2-band PLL circuit and the corresponding reference carrier signal of the PLL circuit, wherein each said L2-band PLL circuit varies the output phase of its reference carrier generator in response to the loop control signal U_K,L2;

a plurality M of generators which generate corresponding correction signals for the L2-band PLL circuits, the correction signal for each L2-band PLL circuit being generated in proportion to at least the L1-band PLL loop control signal U_K,L1 from a PLL circuit which is tracking the corresponding L1-band satellite signal, said correction signal being provided to the corresponding L2-band PLL circuit, and wherein said L2-band PLL circuit modifies the output phase of its the reference carrier generator in response to the correction signal; and

one additional common tracking loop responsive to the phase output signals of said plurality M of tracking channels for the L2-band satellite signals, said additional common tracking loop detects a common phase shift in the phase output signals said plurality of M tracking channels and generates an L2-band phase correction signal Uq_,L2 in response to the detected common phase shift, said additional common tracking loop further varies the output phase of the reference carrier generator of at least one L2-band PLL circuit in response to the value of said L2-band phase correction signal Uq_,L2.